Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - AD converter (ADC) External , Internal LQFP 64

f =

-3dB

ln(2)

2 tp ´

CONV

V =

REF

Range (Code+1)´

1024

ADS8556

ADS8557

ADS8558

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SBAS404B –OCTOBER 2006– REVISED JANUARY 2012

BUSY/INT

Table 1 lists some examples of internal reference

DAC settings with a reference range set to 2.5V.

The BUSY signal indicates if a conversion is in

However, to ensure proper performance, the DAC

progress. It goes high with a rising edge of any

output voltage should not be programmed below

CONVST_x signal and goes low when the output

0.5V.

data of the last channel pair are available in the

respective output register. The readout of the data

The buffered output of the DAC should be decoupled

can be initiated immediately after the falling edge of

with a 100nF capacitor (minimum); for best

BUSY. A falling edge of a CONVST_x input during an

performance, a 470nF capacitor is recommended. If

ongoing conversion (when BUSY is high) powers

the internal reference is placed into power-down

down the corresponding ADC pair.

(default), an external reference voltage can drive the

REFIO pin.

In sequential mode, the BUSY signal goes low only

for one clock cycle. See the Sequential Mode section

The voltage at the REFIO pin is buffered with three

for more details.

internal amplifiers, one for each ADC pair. The output

of each buffer needs to be decoupled with a 10μF

The polarity of the BUSY/INT signal can be changed

capacitor between pin pairs 53 and 54, 55 and 56,

using CR bit C20.

and 57 and 58. The 10μF capacitors are available as

ceramic 0805-SMD components and in X5R quality.

Reference

The internal reference buffers can be powered down

The ADS8556/7/8 provides an internal, low-drift 2.5V

to decrease the power dissipation of the device. In

reference source. To increase the input voltage

this case, external reference drivers can be

range, the reference voltage can be switched to 3V

connected to REFC_A, REFC_B, and REFC_C pins.

mode using the VREF bit (bit C18 in the CR). The

With 10μF decoupling capacitors, the minimum

reference feeds a 10-bit string-DAC controlled by bits

required bandwidth can be calculated using

C[9:0] in the control register. The buffered DAC

Equation 4:

output is connected to the REFIO pin. In this way, the

voltage at this pin is programmable in 2.44mV

(2.92mV in 3V mode) steps and adjustable to the

(4)

application needs without additional external

With the minimum t

CONV

of 1.09μs, the external

components. The actual output voltage can be

reference buffers require a minimum bandwidth of

calculated using Equation 3:

102kHz.

Table 1. DAC Setting Examples (2.5V Operation)

where:

DECIMAL BINARY HEXADECIMAL

REF OUT

(V)

CODE CODE CODE

Range = the chosen maximum reference voltage

0.500 204 00 1100 1100 CC

output range (2.5V or 3V),

1.25 511 01 1111 1111 1FF

Code = the decimal value of the DAC register

content (3)

2.500 1023 11 1111 1111 3FF