Datasheet
Table Of Contents
- FEATURES
- APPLICATIONS
- DESCRIPTION
- ABSOLUTE MAXIMUM RATINGS
- THERMAL INFORMATION
- ELECTRICAL CHARACTERISTICS: ADS7947 (12-Bit)
- ELECTRICAL CHARACTERISTICS: ADS7948 (10-Bit)
- ELECTRICAL CHARACTERISTICS: ADS7949 (8-Bit)
- TIMING DIAGRAM
- TIMING REQUIREMENTS
- PIN CONFIGURATION
- TYPICAL CHARACTERISTICS: ADS7947, ADS7948, ADS7949
- TYPICAL CHARACTERISTICS: ADS7947 (12-Bit)
- OVERVIEW
- DEVICE OPERATION
- APPLICATION INFORMATION
ADS7947
ADS7948
ADS7949
www.ti.com
SLAS708 –SEPTEMBER 2010
ELECTRICAL CHARACTERISTICS: ADS7948 (10-Bit)
Minimum/maximum specifications at AVDD = 2.7V to 5.5V, DVDD = 1.65V to AVDD, T
A
= –40°C to +125°C, and
f
SAMPLE
= 2MSPS, unless otherwise noted. Typical specifications at AVDD = 3V, DVDD = 1.8V, T
A
= +25°C, and f
SAMPLE
=
2MSPS.
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
ANALOG INPUT
Full-scale input span
(1)
AINxP – AINxN 0 V
REF
V
AIN0P, AIN1P –0.2 AVDD + 0.2 V
Absolute input range
AIN0N, AIN1N –0.2 0.2 V
Input capacitance
(2)
32 pF
Input leakage current At +125°C 1.5 nA
SYSTEM PERFORMANCE
Resolution 10 Bits
No missing codes 10 Bits
Integral linearity –0.5 ±0.15 0.5 LSB
(3)
Differential linearity –0.5 ±0.15 0.5 LSB
Offset error
(4)
–0.5 ±0.15 0.5 LSB
Gain error –0.5 ±0.15 0.5 LSB
Transition noise 25 µV
RMS
Power-supply rejection 60 dB
SAMPLING DYNAMICS
Conversion time 10.5 SCLK
Acquisition time 80 ns
Maximum sample rate (throughput rate) 34MHz SCLK in 16-clock frame 2 MSPS
34MHz SCLK and CS low for 10.5 clocks 2.57 MSPS
Aperture delay 5 ns
Aperture jitter 10 ps
Step response 80 ns
Overvoltage recovery 80 ns
DYNAMIC CHARACTERISTICS
Total harmonic distortion (THD)
(5)
100kHz –80 dB
Signal-to-noise ratio (SNR) 100kHz 61 dB
Signal-to-noise and distortion ratio (SINAD) 100kHz 61 dB
Spurious-free dynamic range (SFDR) 100kHz 81 dB
Full-power bandwidth At –3dB 15 MHz
DIGITAL INPUT/OUTPUT
Logic family CMOS
V
IH
0.7DVDD V
V
IL
0.3DVDD V
Logic level
V
OH
I
SOURCE
= 200µA DVDD – 0.2 V
V
OL
I
SINK
= 200µA 0.4 V
Input leakage current I
IH
, I
IL
0 < V
IN
< DVDD ±20 nA
External reference 2.5 AVDD V
(1) Ideal input span; does not include gain or offset error.
(2) Refer to Figure 39 for sampling circuit details.
(3) LSB means Least Significant Bit.
(4) Measured relative to an ideal full-scale input.
(5) Calculated on the first nine harmonics of the input frequency.
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Product Folder Link(s): ADS7947 ADS7948 ADS7949