Datasheet

ADS7828
5
SBAS181C
www.ti.com
PARAMETER SYMBOL CONDITIONS MIN MAX UNITS
SCL Clock Frequency f
SCL
Standard Mode 100 kHz
Fast Mode 400 kHz
High-Speed Mode, C
B
= 100pF max 3.4 MHz
High-Speed Mode, C
B
= 400pF max 1.7 MHz
Bus Free Time Between a STOP and t
BUF
Standard Mode 4.7 µs
START Condition Fast Mode 1.3 µs
Hold Time (Repeated) START t
HD
;
STA
Standard Mode 4.0 µs
Condition Fast Mode 600 ns
High-Speed Mode 160 ns
LOW Period of the SCL Clock t
LOW
Standard Mode 4.7 µs
Fast Mode 1.3 µs
High-Speed Mode, C
B
= 100pF max
(2)
160 ns
High-Speed Mode, C
B
= 400pF max
(2)
320 ns
HIGH Period of the SCL Clock t
HIGH
Standard Mode 4.0 µs
Fast Mode 600 ns
High-Speed Mode, C
B
= 100pF max
(2)
60 ns
High-Speed Mode, C
B
= 400pF max
(2)
120 ns
Setup Time for a Repeated START t
SU
;
STA
Standard Mode 4.7 µs
Condition Fast Mode 600 ns
High-Speed Mode 160 ns
Data Setup Time t
SU
;
DAT
Standard Mode 250 ns
Fast Mode 100 ns
High-Speed Mode 10 ns
Data Hold Time t
HD
;
DAT
Standard Mode 0 3.45 µs
Fast Mode 0 0.9 µs
High-Speed Mode, C
B
= 100pF max
(2)
0
(3)
70 ns
High-Speed Mode, C
B
= 400pF max
(2)
0
(3)
150 ns
Rise Time of SCL Signal t
RCL
Standard Mode 1000 ns
Fast Mode 20 + 0.1C
B
300 ns
High-Speed Mode, C
B
= 100pF max
(2)
10 40 ns
High-Speed Mode, C
B
= 400pF max
(2)
20 80 ns
Rise Time of SCL Signal After a t
RCL1
Standard Mode 1000 ns
Repeated START Condition and Fast Mode 20 + 0.1C
B
300 ns
After an Acknowledge Bit High-Speed Mode, C
B
= 100pF max
(2)
10 80 ns
High-Speed Mode, C
B
= 400pF max
(2)
20 160 ns
Fall Time of SCL Signal t
FCL
Standard Mode 300 ns
Fast Mode 20 + 0.1C
B
300 ns
High-Speed Mode, C
B
= 100pF max
(2)
10 40 ns
High-Speed Mode, C
B
= 400pF max
(2)
20 80 ns
TIMING CHARACTERISTICS
(1)
At T
A
= –40°C to +85°C, +V
DD
= +2.7V, unless otherwise noted.
TIMING DIAGRAM
t
R
t
BUF
t
LOW
t
F
t
HD; STA
t
SP
t
HD; STA
t
SU; STA
t
HD; DAT
t
SU; DAT
t
HIGH
t
SU; STO
SCL
SDA
START REPEATED
START
STOP
NOTES: (1) All values referred to V
IHMIN
and V
ILMAX
levels.
(2) For bus line loads C
B
between 100pF and 400pF the timing parameters must be linearly interpolated.
(3) A device must internally provide a data hold time to bridge the undefined part between V
IH
and V
IL
of the falling edge of the SCLH signal. An
input circuit with a threshold as low as possible for the falling edge of the SCLH signal minimizes this hold time.