Datasheet

R
100W
SER
R
100W
SW
R
100W
SER
R
100W
SW
5pF
C
PAR
C
5pF
PAR
CH +xx
CHxx-
40pF
C
S
C
40pF
S
AVDD
AVDD
AGND
AGND
Input
Mux
CHx1P/CHx3
CHx1N/CHx2
CHx0P/CHx1
CHx0N/CHx0
To
ADC
ADS8363
ADS7263
ADS7223
SBAS523B –OCTOBER 2010–REVISED JANUARY 2011 www.ti.com
THEORY OF OPERATION
GENERAL DESCRIPTION
Channel selection is performed using either the
external M0 pin or the C[1:0] bits in the Configuration
The ADS8363/7263/7223 contain two 16-/14-/12-bit
(CONFIG) register in fully-differential mode, or using
analog-to-digital converters (ADCs), respectively, that
the SEQFIFO register in pseudo-differential mode. In
operate based on the successive approximation
either case, changing the multiplexer settings impacts
register (SAR) principle. These ADCs sample and
the conversion started with the next CONVST pulse.
convert simultaneously. Conversion time can be as
low as 875ns. Adding an acquisition time of 100ns,
Table 1. Fully-Differential 2:1 Multiplexer
and a margin of 25ns for propagation delay and
Configuration
CONVST pulse generation, results in a maximum
conversion rate of 1MSPS.
C1 C0 ADC+ ADC–
0 x CHx0P CHx0N
Each ADC has a fully-differential 2:1 multiplexer
1 x CHx1P CHx1N
front-end. In many common applications, all negative
input signals remain at the same constant voltage (for
example, 2.5V). For these applications, the
Table 2. Pseudo-Differential 4:1 Multiplexer
multiplexer can be used in a pseudo-differential 4:1
Configuration
mode, where the CMx pins function as
C1 C0 ADC+ ADC–
common-mode pins and all four analog inputs are
0 0 CHx0 CMx/REFIOx
referred to the corresponding CMx pin.
0 1 CHx1 CMx/REFIOx
The ADS8363/7263/7223 also include a 2.5V internal
1 0 CHx2 CMx/REFIOx
reference. This reference drives two
1 1 CHx3 CMx/REFIOx
independently-programmable, 10-bit digital-to-analog
converters (DACs), allowing the voltage at each of
The input path for the converter is fully differential
the REFIOx pins to be adjusted through the internal
and provides a good common-mode rejection of 92dB
REFDACx registers in 2.44mV steps. A low-noise,
at 100kHz (for the ADS8363). The high CMRR also
unity-gain operational amplifier buffers each of the
helps suppress noise in harsh industrial
DAC outputs and drives the REFIOx pin.
environments.
The ADS8363/7263/7223 provide a serial interface
Each of the 40pF sample-and-hold capacitors (shown
that is compatible with the ADS8361. However,
as C
S
in Figure 28) is connected through switches to
instead of the ADS8361 A0 pin that controls the
the multiplexer output. Opening the switches holds
channel selection, the ADS8363/7263/7223 offers a
the sampled data during the conversion process.
serial data input (SDI) pin that supports additional
After the conversion completes, both capacitors are
functions described in the Digital section of this data
precharged for the duration of one clock cycle to the
sheet (also see the ADS8361 Compatibility section).
voltage present at the REFIOx pin. After precharging,
the multiplexer outputs are connected to the sampling
ANALOG
capacitors again. The voltage at the analog input pin
This section discusses the analog input circuit, the
is usually different from the reference voltage;
ADCs, and the reference design of the device.
therefore, the sample capacitors must be charged to
within one-half LSB for 16-, 14-, or 12-bit accuracy
Analog Inputs
during the acquisition time t
ACQ
(see the Timing
Diagrams).
Each ADC is fed by an input multiplexer, as shown in
Figure 27. Each multiplexer is used in either a
fully-differential 2:1 configuration (as shown in
Table 1) or a pseudo-differential 4:1 configuration (as
shown in Table 2).
Figure 28. Equivalent Analog Input Circuit
Figure 27. Input Multiplexer Configuration
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