Datasheet

t
H1
t
SU1
t
H2
t
SU2
LCLK
N
LCLK
P
OUT
N
OUT
P
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11
Sample n
Sample n+12
t
PROP
t (A)
D
12clockslatency
AnalogInput
ClockInput
6XADCLK
LCLK
N
LCLK
P
1XADCLK
ADCLK
N
ADCLK
P
SERIAL DATA
OUT
P
OUT
N
t
SAMPLE
Sample n+13
ADS5281
ADS5282
SBAS397I –DECEMBER 2006–REVISED JUNE 2012 www.ti.com
LVDS TIMING DIAGRAM
DEFINITION OF SETUP AND HOLD TIMES
t
SU
= min(t
SU1
, t
SU2
)
t
H
= min(t
H1
, t
H2
)
TIMING CHARACTERISTICS
(1) (2)
ADS528x
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
A
Aperture delay 1.5 4.5 ns
Aperture delay variation Channel-to-channel within the same device (3σ) ±20 ps
t
J
Aperture jitter 400 fs
Time to valid data after coming out of
50 μs
COMPLETE POWER-DOWN mode
Time to valid data after coming out of PARTIAL
t
WAKE
Wake-up time POWER-DOWN mode (with clock continuing to 2 μs
run during power-down)
Time to valid data after stopping and restarting
40 μs
the input clock
Clock
Data latency 12
cycles
(1) Timing characteristics are common to the ADS528x family.
(2) Timing parameters are ensured by design and characterization; not production tested.
12 Copyright © 2006–2012, Texas Instruments Incorporated