Datasheet

ADS131E04

ADS131E06

ADS131E08

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SBAS561A –JUNE 2012–REVISED APRIL 2013

SPI INTERFACE

The SPI-compatible serial interface consists of four signals: CS, SCLK, DIN, and DOUT. The interface reads

conversion data, reads and writes registers, and controls the ADS131E0x operation. The DRDY output is used

as a status signal to indicate when data are ready. DRDY goes low when new data are available.

Chip Select (CS)

Chip select (CS) selects the ADS131E0x for SPI communication. CS must remain low for the entire serial

communication duration. After the serial communication is finished, four or more t

CLK

cycles must elapse before

taking CS high. When CS is taken high, the serial interface is reset, SCLK and DIN are ignored, and DOUT

enters a high-impedance state. DRDY asserts when data conversion is complete, regardless of whether CS is

high or low.

Serial Clock (SCLK)

SCLK is the serial peripheral interface (SPI) serial clock. It is used to shift in commands and shift out data from

the device. The serial clock (SCLK) features a Schmitt-triggered input and clocks data on the DIN and DOUT

pins into and out of the ADS131E0x.

Care should be taken to prevent glitches on SCLK while CS is low. Glitches as small as 1 ns wide could be

interpreted as a valid serial clock. After eight serial clock events, the ADS131E0x assume an instruction must be

interrupted and executed. If it is suspected that instructions are being interrupted erroneously, toggle CS high

and back low to return the chip to normal operation. It is also recommended to issue serial clocks in multiples of

eight. The absolute maximum SCLK limit is specified in the Serial Interface Timing table.

For a single device, the minimum speed needed for SCLK depends on the number of channels, number of bits of

resolution, and output data rate. (For multiple cascaded devices, see the Standard Mode subsection of the

Multiple Device Configuration section.) The SCLK rate limitation, as described by Equation 6, applies to RDATAC

mode.

SCLK

< (t

– 4 t

CLK

) / (N

BITS

CHANNELS

+ 24) (6)

For example, if the ADS131E0x is used in an 8-kSPS mode (eight channels, 24-bit resolution), the minimum

SCLK speed is 1.72 MHz.

Data retrieval can be done either by putting the device in RDATAC mode or by issuing an RDATA command for

data on demand. The SCLK rate limitation, as described by Equation 6, applies to RDATAC mode. For the

RDATA command, the limitation applies if data must be read in between two consecutive DRDY signals. The

above calculation assumes that there are no other commands issued in between data captures.

Data Input (DIN)

The data input pin (DIN) is used along with SCLK to communicate with the ADS131E0x (opcode commands and

Product Folder Links: ADS131E04 ADS131E06 ADS131E08