Datasheet

 2010-2016 Microchip Technology Inc. DS40001412G-page 445
PIC18(L)F2X/4XK22
FIGURE 27-17: I
2
C BUS START/STOP BITS TIMING
TABLE 27-14: SPI MODE REQUIREMENTS
Param.
No.
Symbol Characteristic Min Max Units Conditions
70 TssL2scH,
TssL2scL
SS
 to SCK  or SCK  Input TCY —ns
71 TscH
SCK Input High Time Continuous 25 — ns
72 TscL
SCK Input Low Time Continuous 30 — ns
73 TdiV2scH,
TdiV2scL
Setup Time of SDI Data Input to SCK Edge 25 — ns
74 TscH2diL,
TscL2diL
Hold Time of SDI Data Input to SCK Edge 25 — ns
75 TdoR
SDO Data Output Rise Time — 30 ns
76 TdoF
SDO Data Output Fall Time — 20 ns
77 TssH2doZ SS
 to SDO Output High-Impedance 10 50 ns
78 TscR
SCK Output Rise Time
(Master mode)
—30ns
79 TscF
SCK Output Fall Time (Master mode) — 20 ns
80 TscH2doV,
TscL2doV
SDO Data Output Valid after SCK Edge — 20
60
ns
ns
SPI Master Mode
SPI Slave Mode
81 TdoV2scH,
TdoV2scL
SDO Data Output Setup to SCK Edge T
CY —ns
82 TssL2doV SDO Data Output Valid after SS
 Edge — 60 ns
83 TscH2ssH,
TscL2ssH
SS
 after SCK edge 1.5 TCY + 40 — ns
Note: Refer to Figure 27-6 for load conditions.
91
92
93
SCL
SDA
Start
Condition
Stop
Condition
90