Datasheet

 2010-2016 Microchip Technology Inc. DS40001412G-page 205
PIC18(L)F2X/4XK22
The I
2
C interface supports the following modes and
features:
•Master mode
• Slave mode
• Byte NACKing (Slave mode)
• Limited Multi-master support
• 7-bit and 10-bit addressing
• Start and Stop interrupts
• Interrupt masking
• Clock stretching
• Bus collision detection
• General call address matching
•Address masking
• Address Hold and Data Hold modes
• Selectable SDAx hold times
Figure 15-2 is a block diagram of the I
2
C interface
module in Master mode. Figure 15-3 is a diagram of the
I
2
C interface module in Slave mode.
The PIC18(L)F2X/4XK22 has two MSSP modules,
MSSP1 and MSSP2, each module operating
independently from the other.
FIGURE 15-2: MSSPx BLOCK DIAGRAM (I
2
C MASTER MODE)
Note 1: In devices with more than one MSSP
module, it is very important to pay close
attention to SSPxCONx register names.
SSP1CON1 and SSP1CON2 registers
control different operational aspects of
the same module, while SSP1CON1 and
SSP2CON1 control the same features for
two different modules.
2: Throughout this section, generic
references to an MSSP module in any of
its operating modes may be interpreted
as being equally applicable to MSSP1 or
MSSP2. Register names, module I/O
signals, and bit names may use the
generic designator ‘x’ to indicate the use
of a numeral to distinguish a particular
module when required.
Read Write
SSPxSR
Start bit, Stop bit,
Start bit Detect,
SSPxBUF
Internal
Data Bus
Set/Reset: S, P, SSPxSTAT, WCOL, SSPxOV
Shift
Clock
MSb
LSb
SDAx
Acknowledge
Generate (SSPxCON2)
Stop bit Detect
Write Collision Detect
Clock Arbitration
State Counter for
end of XMIT/RCV
SCLx
SCLx in
Bus Collision
SDAx in
Receive Enable (RCEN)
Clock Cntl
Clock Arbitrate/BCOL Detect
(Hold off clock source)
[SSPxM 3:0]
Baud Rate
Reset SEN, PEN (SSPxCON2)
Generator
(SSPxADD)
Address Match Detect
Set SSPxIF, BCLxIF