Datasheet

PIC18(L)F2X/4XK22
DS40001412G-page 178  2010-2016 Microchip Technology Inc.
14.2.4 SPECIAL EVENT TRIGGER
When Special Event Trigger mode is selected
(CCPxM<3:0> = 1011), and a match of the
TMRxH:TMRxL and the CCPRxH:CCPRxL registers
occurs, all CCPx and ECCPx modules will immediately:
• Set the CCP interrupt flag bit – CCPxIF
• CCP5 will start an ADC conversion, if the ADC is
enabled
On the next TimerX rising clock edge:
• A Reset of TimerX register pair occurs –
TMRxH:TMRxL = 0x0000,
This Special Event Trigger mode does not:
• Assert control over the CCPx or ECCPx pins.
• Set the TMRxIF interrupt bit when the
TMRxH:TMRxL register pair is reset. (TMRxIF
gets set on a TimerX overflow.)
If the value of the CCPRxH:CCPRxL registers are
modified when a match occurs, the user should be
aware that the automatic reset of TimerX occurs on the
next rising edge of the clock. Therefore, modifying the
CCPRxH:CCPRxL registers before this reset occurs
will allow the TimerX to continue without being reset,
inadvertently resulting in the next event being
advanced or delayed.
The Special Event Trigger mode allows the
CCPRxH:CCPRxL register pair to effectively provide a
16-bit programmable period register for TimerX.
14.2.5 COMPARE DURING SLEEP
The Compare mode is dependent upon the system
clock (F
OSC) for proper operation. Since FOSC is shut
down during Sleep mode, the Compare mode will not
function properly during Sleep.
TABLE 14-5: REGISTERS ASSOCIATED WITH COMPARE
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Register
on Page
CCP1CON
P1M<1:0> DC1B<1:0> CCP1M<3:0>
198
CCP2CON P2M<1:0> DC2B<1:0> CCP2M<3:0>
198
CCP3CON
P3M<1:0> DC3B<1:0> CCP3M<3:0>
198
CCP4CON
— — DC4B<1:0> CCP4M<3:0>
198
CCP5CON
— — DC5B<1:0> CCP5M<3:0>
198
CCPR1H Capture/Compare/PWM Register 1 High Byte (MSB)
—
CCPR1L Capture/Compare/PWM Register 1 Low Byte (LSB)
—
CCPR2H Capture/Compare/PWM Register 2 High Byte (MSB)
—
CCPR2L Capture/Compare/PWM Register 2 Low Byte (LSB)
—
CCPR3H Capture/Compare/PWM Register 3 High Byte (MSB)
—
CCPR3L Capture/Compare/PWM Register 3 Low Byte (LSB)
—
CCPR4H Capture/Compare/PWM Register 4 High Byte (MSB)
—
CCPR4L Capture/Compare/PWM Register 4 Low Byte (LSB)
—
CCPR5H Capture/Compare/PWM Register 5 High Byte (MSB)
—
CCPR5L Capture/Compare/PWM Register 5 Low Byte (LSB)
—
CCPTMRS0 C3TSEL<1:0>
— C2TSEL<1:0> — C1TSEL<1:0>
201
CCPTMRS1
— — — — C5TSEL<1:0> C4TSEL<1:0>
201
INTCON GIE/GIEH PEIE/GIEL
TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF
109
IPR1 — ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP
121
Legend: — = Unimplemented location, read as ‘0’. Shaded bits are not used by Compare mode.
Note 1: These registers/bits are available on PIC18(L)F4XK22 devices.