Datasheet

PIC18(L)F2X/4XK22
DS40001412G-page 142  2010-2016 Microchip Technology Inc.
TABLE 10-11: PORTD I/O SUMMARY
Pin Name Function
TRIS
Setting
ANSEL
setting
Pin
Type
Buffer
Type
Description
RD0/SCK2/SCL2/AN20 RD0 00O DIG LATD<0> data output; not affected by analog input.
10I ST PORTD<0> data input; disabled when analog input
enabled.
SCK2 00O DIG MSSP2 SPI Clock output.
10I ST MSSP2 SPI Clock input.
SCL2 00ODIGMSSP2 I
2
C Clock output.
10II
2
C MSSP2 I
2
C Clock input.
AN20 11I AN Analog input 20.
RD1/CCP4/SDI2/SDA2/
AN21
RD1 00O DIG LATD<1> data output; not affected by analog input.
10I ST PORTD<1> data input; disabled when analog input
enabled.
CCP4 00O DIG Compare 4 output/PWM 4 output.
10I ST Capture 4 input.
SDI2 10I ST MSSP2 SPI data input.
SDA2 00ODIGMSSP2 I
2
C data output.
10II
2
C MSSP2 I
2
C data input.
AN21 11I AN Analog input 21.
RD2/P2B/AN22 RD2 00O DIG LATD<2> data output; not affected by analog input.
10I ST PORTD<2> data input; disabled when analog input
enabled.
P2B
(1)
00O DIG Enhanced CCP2 PWM output 2.
AN22 11I AN Analog input 22.
RD3/P2C/SS2
/AN23 RD3 00O DIG LATD<3> data output; not affected by analog input.
10I ST PORTD<3> data input; disabled when analog input
enabled.
P2C 00O DIG Enhanced CCP2 PWM output 4.
S
S2 10I TTL MSSP2 SPI slave select input.
AN23 11I AN Analog input 23.
RD4/P2D/SDO2/AN24 RD4 00O DIG LATD<4> data output; not affected by analog input.
10I ST PORTD<4> data input; disabled when analog input
enabled.
P2D 00O DIG Enhanced CCP2 PWM output 3.
SDO2 00O DIG MSSP2 SPI data output.
AN24 11I AN Analog input 24.
RD5/P1B/AN25 RD5 00O DIG LATD<5> data output; not affected by analog input.
10I ST PORTD<5> data input; disabled when analog input
enabled.
P1B 00O DIG Enhanced CCP1 PWM output 2.
AN25 11I AN Analog input 25.
Legend: AN = Analog input or output; TTL = TTL compatible input; HV = High Voltage; OD = Open Drain; XTAL = Crystal; CMOS =
CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I
2
C = Schmitt Trigger input with I
2
C.
Note 1: Default pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and
CCP2MX are set.