Datasheet

MAX5813/MAX5814/MAX5815
Ultra-Small, Quad-Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and I
2
C Interface
15Maxim Integrated
Clear Input (CLR)
The MAX5813/MAX5814/MAX5815 feature an asynchro-
nous active-low CLR logic input that simultaneously sets
all four DAC outputs to zero. Driving CLR low clears the
contents of both the CODE and DAC registers and also
aborts the on-going I
2
C command. To allow a new I
2
C
command, drive CLR high, satisfying the t
CLRSTA
timing
requirement.
Interface Power Supply (V
DDIO
)
The MAX5813/MAX5814/MAX5815 feature a separate
supply pin (V
DDIO
) for the digital interface (1.8V to 5.5V).
Connect V
DDIO
to the I/O supply of the host processor.
I
2
C Serial Interface
The MAX5813/MAX5814/MAX5815 feature an I
2
C-/
SMBusK-compatible, 2-wire serial interface consisting of
a serial data line (SDA) and a serial clock line (SCL). SDA
and SCL enable communication between the MAX5813/
MAX5814/MAX5815 and the master at clock rates up
to 400kHz. Figure 1 shows the 2-wire interface timing
diagram. The master generates SCL and initiates data
transfer on the bus. The master device writes data to the
MAX5813/MAX5814/MAX5815 by transmitting the proper
slave address followed by the command byte and then
the data word. Each transmit sequence is framed by a
START (S) or Repeated START (Sr) condition and a STOP
(P) condition. Each word transmitted to the MAX5813/
MAX5814/MAX5815 is 8 bits long and is followed by an
acknowledge clock pulse. A master reading data from
the MAX5813/MAX5814/MAX5815 must transmit the
proper slave address followed by a series of nine SCL
pulses for each byte of data requested. The MAX5813/
MAX5814/MAX5815 transmit data on SDA in sync with
the master-generated SCL pulses. The master acknowl-
edges receipt of each byte of data. Each read sequence
is framed by a START or Repeated START condition, a
not acknowledge, and a STOP condition. SDA operates
as both an input and an open-drain output. A pullup
resistor, typically 4.7kI is required on SDA. SCL oper-
ates only as an input. A pullup resistor, typically 4.7kI, is
required on SCL if there are multiple masters on the bus,
or if the single master has an open-drain SCL output.
Series resistors in line with SDA and SCL are optional.
Series resistors protect the digital inputs of the MAX5813/
MAX5814/MAX5815 from high voltage spikes on the bus
lines and minimize crosstalk and undershoot of the bus
signals. The MAX5813/MAX5814/MAX5815 can accom-
modate bus voltages higher than V
DDIO
up to a limit of
5.5V; bus voltages lower than V
DDIO
are not recommend-
ed and may result in significantly increased interface cur-
rents. The MAX5813/MAX5814/MAX5815 digital inputs
are double buffered. Depending on the command issued
through the serial interface, the CODE register(s) can
be loaded without affecting the DAC register(s) using
the write command. To update the DAC registers, either
drive the LDAC input low to asynchronously update all
DAC outputs, or use the software LOAD command.
I
2
C START and STOP Conditions
SDA and SCL idle high when the bus is not in use. A mas-
ter initiates communication by issuing a START condition.
A START condition is a high-to-low transition on SDA with
SCL high. A STOP condition is a low-to-high transition
on SDA while SCL is high (Figure 2). A START condition
from the master signals the beginning of a transmission
Figure 2. I
2
C START, Repeated START, and STOP Conditions
SMBus is a trademark of Intel Corp.
Figure 2
SCL
SDA
SS
rP
VALID START, REPEATED START, AND STOP PULSES
PS PSPPS
INVALID START/STOP PULSE PAIRINGS -ALL WILL BE RECOGNIZED AS STARTS