Datasheet

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MAX3946
1Gbps to 11.3Gbps, SFP+ Laser Driver
with Laser Impedance Mismatch Tolerance
Detailed Description
The MAX3946 SFP+ laser driver is designed to drive
5I to 50I TOSAs from 1Gbps to 11.3Gbps. The device
contains an input buffer with programmable equaliza-
tion, pulse-width adjustment, bias current and modula-
tion current DACs, output driver with programmable
deemphasis, power-on reset circuitry, bias monitor, laser
current limiter, and eye-safety circuitry. A 3-wire digital
interface is used to control the transmitter functions.
The registers that control the device’s functionality are
TXCTRL, SET_IMOD, SET_IBIAS, IMODMAX, IBIASMAX,
MODINC, BIASINC, SET_TXEQ, SET_PWCTRL, and
SET_TXDE.
Input Buffer with Programmable
Equalization
The input is internally biased and terminated with 50I to
a common-mode voltage. The first amplifier stage fea-
tures a programmable equalizer for high-frequency loss-
es including SFP connector. Equalization is controlled
by the SET_TXEQ register and TXEQ_EN bit, TXCTRL[3]
(Table 1). The TX_POL bit in the TXCTRL register con-
trols the polarity of TOUT+ and TOUT- vs. TIN+ and TIN-.
The SET_PWCTRL register controls the output eye cross-
ing (Table 5). A status indicator bit (TXED) monitors the
presence of an AC input signal.
Bias Current DAC
The device’s bias current is optimized to provide up
to 80mA of bias current into a 5I to 50I laser load
with 200FA resolution. The bias current is controlled
through the 3-wire digital interface using the SET_IBIAS,
IBIASMAX, and BIASINC registers.
For laser operation, the laser bias current can be set
using the 9-bit SET_IBIAS DAC. The upper 8 bits are set
by the SET_IBIAS[8:1] register, commonly used during
the initialization procedure after POR. The LSB (bit 0)
of SET_IBIAS is initialized to zero after POR and can
be updated using the BIASINC register. The IBIASMAX
register should be programmed to a desired maximum
bias current value (up to 96mA) to protect the laser. The
IBIASMAX register limits the maximum SET_IBIAS[8:1]
DAC code.
After initialization the value of the SET_IBIAS DAC reg-
ister should be updated using the BIASINC register
to optimize cycle time and enhance laser safety. The
BIASINC register is an 8-bit register where the first 5
bits contain the increment information in two’s comple-
ment notation. Increment values range from -16 to +15
LSBs. If the updated value of SET_IBIAS[8:1] exceeds
IBIASMAX[7:0], the IBIASERR warning flag is set and
SET_IBIAS[8:0] remains unchanged.
Modulation Current DAC
The modulation current from the device is optimized to
provide up to 80mA of modulation current into a 5I to
25I differential laser load (60mA for 50I laser load)
with 300FA to 200FA resolution. The modulation current
is controlled through the 3-wire digital interface using
the SET_IMOD, IMODMAX, MODINC, and SET_TXDE
registers.
For laser operation, the laser modulation current can be
set using the 9-bit SET_IMOD DAC. The upper 8 bits
are set by the SET_IMOD[8:1] register, commonly used
during the initialization procedure after POR. The LSB (bit 0)
of SET_IMOD is initialized to zero after POR and can
be updated using the MODINC register. The IMODMAX
register should be programmed to a desired maximum
modulation current value (up to 96mA) to protect the
laser. The IMODMAX register limits the maximum
SET_IMOD[8:1] DAC code.
Table 1. Input Equalization Control Register Settings
TXCTRL[3]
SET_TXEQ[2:1] DESCRIPTION
TXEQ_EN
0 X X 150mV
P-P
to 1000mV
P-P
differential input amplitude (default setting)
1 0 0 Optimized for 1in to 4in FR4, 190mV
P-P
to 450mV
P-P
differential launch amplitude from source
1 0 1 Optimized for 4in to 6in FR4, 190mV
P-P
to 450mV
P-P
differential launch amplitude from source
1 1 0 Optimized for 1in to 4in FR4, 450mV
P-P
to 700mV
P-P
differential launch amplitude from source
1 1 1 Optimized for 4in to 6in FR4, 450mV
P-P
to 700mV
P-P
differential launch amplitude from source