Datasheet

MAX153 1Msps, µP-Compatible,
8-Bit ADC with 1µA Power-Down
www.maximintegrated.com
Maxim Integrated │ 9
Fastest Conversion: Reading Before Delay
An external method of controlling the conversion time is
shown in Figure 5. The internally generated delay t
INTL
varies slightly with temperature and supply voltage, and can
be overridden with RD to achieve the fastest conversion
time. INT is ignored, and RD is brought low typically 250ns
after the rising edge of WR. This completes the conversion
and enables the output buffers (D0–D7) that contain the
conversion result. INT also goes low after the falling edge
of RD and is reset on the rising edge of RD or CS. The total
conversiontimeistherefore:
t
CWR
= t
WR
(250ns) + t
CSH
(0ns) to t
RD
(250ns) + t
ACC1
(160ns) = 660ns.
Pipelined Operation
Besides the two standard WR-RD mode options, pipe-
lined operation can be achieved by connecting WR and
RDtogether(Figure6).WithCS low, driving WR and RD
low initiates a conversion and reads the result of the previ-
ous conversion concurrently.
Analog Considerations
Reference
Figures7a–7cshowsomereferenceconnections.V
REF+
and V
REF-
inputs set the full-scale and zero-input voltages
of the ADC. The voltage at V
REF-
defines the input that
produces an output code of all zeros, and the voltage at
V
REF+
defines the input that produces an output code of
all ones.
Figure 3. RD Mode Timing (MODE = 0)
Figure 5. WR-RD Mode Timing (t
RD
> t
INTL
), Fastest Operating
Mode (MODE = 1)
Figure 4. WR-RD Mode Timing (t
RD
> t
INTL
) (MODE = 1) Figure 6. Pipelined Mode Timing (WR = RD) (MODE = 1)
t
P
t
INTH
t
CSH
t
DH
t
CRD
t
ACC0
WITH EXTERNAL PULLUP
t
CSS
t
RDY
CS
RD
INT
D0–D
7V
ALID DATA
RDY
VALID DATA
t
ACC2
t
DH
t
INTH
t
CSH
t
WR
t
CSS
CS
WR
INT
D0–D7
RD
t
RD
t
P
t
READ2
t
INTL
t
CWR
t
CSH
t
P
t
RD
t
CSS
t
RI
t
READ1
t
ACC1
t
DH
t
INTH
t
WR
DATA VALID
CS
WR
RD
INT
D0–D7
t
IHWR
t
ID
t
WR
t
P
NEW DATAOLD DATA
RD, WR
INT
D0–D7
t
INTL