Datasheet

8Maxim Integrated
MAX11329–MAX11332
3Msps, 12-/10-Bit, 8-/16-Channel ADCs with
Post-Mux External Signal Conditioning Access
ELECTRICAL CHARACTERISTICS (MAX11329/MAX11330) (continued)
(V
DD
= 2.35V to 3.6V, V
OVDD
= 1.5V to 3.6V, f
SAMPLE
= 3Msps, f
SCLK
= 48MHz, 50% duty cycle, V
REF+
= V
DD
, T
A
= -40NC to +125NC,
unless otherwise noted. Typical values are at T
A
= +25NC.) (Note 2)
Note 2: Limits are 100% production tested at T
A
= +25NC. Limits over the operating temperature range are guaranteed by design.
Parts are tested with MUX externally connected to the ADC input.
Note 3: Channel ID disabled.
Note 4: Tested in single-ended mode.
Note 5: Offset nulled.
Note 6: Line rejection D(D
OUT
) with V
DD
= 2.35V to 3.6V and V
REF+
= 2.35V.
Note 7:
Tested and guaranteed with fully differential input.
Note 8: Conversion time is defined as the number of clock cycles multiplied by the clock period with a 50% duty cycle.
Maximum conversion time: 1.91Fs + N x 16 x t
OSC_MAX
t
OSC_MAX
= 29.4ns, t
OSC_TYP
= 25ns.
Note 9:
The operational input voltage range for each individual input of a differentially configured pair is from V
DD
to GND. The
operational input voltage difference is from -V
REF+
/2 to +V
REF+
/2 or -V
REF+
to +V
REF+
.
Note 10: See Figure 3 (Equivalent Input Circuit).
Note 11: Guaranteed by characterization.
Figure 1. Detailed Serial-Interface Timing Diagram
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SCLK Rise to DIN Hold t
DH
1 ns
CS Fall to SCLK Fall Setup
t
CSS
4 ns
SCLK Fall to CS Fall Hold
t
CSH
1 ns
CNVST Pulse Width
t
CSW
See Figure 6 5 ns
CS or CNVST Rise to EOC Low
(Note 7)
t
CNV_INT
See Figure 7, f
SAMPLE
= 3Msps 1.7 2.4
Fs
CS Pulse Width
t
CSBW
5 ns
t
CSS
t
CH
t
CP
t
CSH
t
DOT
t
DS
t
DH
t
DOD
t
DOE
CS
SCLK
DIN
DOUT
16TH
CLOCK
1ST
CLOCK
t
CSBW