Datasheet

MAX11120–MAX11128
1Msps, Low-Power, Serial 12-/10-/8-Bit,
4-/8-/16-Channel ADCs
19Maxim Integrated
Figure 2c. External Clock Timing Diagram with CHAN_ID=0
Single-Ended, Differential,
and Pseudo-Differential Input
The MAX11120–MAX11128 include up to 16 analog input
channels that can be configured to 16 single-ended
inputs, 8 fully differential pairs, or 15 pseudo-differential
inputs with respect to one common input (REF-/AIN15 is
the common input).
The analog input range is 0V to V
REF+
in single-ended
and pseudo-differential mode (unipolar) and QV
REF+
/2 or
QV
REF+
in fully differential mode (bipolar) depending on
the RANGE register settings. See Table 7 for the RANGE
register setting.
Unipolar mode sets the differential input range from 0
to V
REF+
. If the positive analog input swings below the
negative analog input in unipolar mode, the digital output
code is zero. Selecting bipolar mode sets the differential
input range to QV
REF+
/2 or QV
REF+
depending on the
RANGE register settings (Table 7).
In single-ended mode, the ADC always operates in uni-
polar mode. The analog inputs are internally referenced
to GND with a full-scale input range from 0 to V
REF+
.
Single-ended conversions are internally referenced to
GND (Figure 3).
The MAX11120–MAX11128 feature 15 pseudo differen-
tial inputs by setting the PDIFF_COM bits in the Unipolar
register to 1 (Table 10). The 15 analog input signals
inputs are referenced to a DC signal applied to the
REF-/AIN15.
Fully Differential Reference (REF+, REF-)
When the reference is used in fully differential mode
(REFSEL = 1), the full-scale range is set by the difference
between REF+ and REF-. The output clips if the input
signal surpasses this reference range.
ADC Transfer Function
The output format of the MAX11120–MAX11128 is straight
binary in unipolar mode and two’s complement in bipolar
mode. The code transitions midway between successive
integer LSB values, such as 0.5 LSB, 1.5 LSB. Figure 4
and Figure 5 show the unipolar and bipolar transfer func-
tion, respectively. Output coding is binary, with 1 LSB =
V
REF+
/4096.
Figure 3. Equivalent Input Circuit
23456781101112131415169
CS
SCLK
DIN
DOUT
0LSBMSB] MSB-1 MSB-2
DI[15] DI[1]
0
DI[0]DI[14]
DAC
COMPARATOR
DAC
AINn
AINn+1
(GND)
HOLD