Datasheet

19Maxim Integrated
DS2484
Single-Channel 1-Wire Master
with Adjustable Timing and Sleep Mode
Figure 7. I
2
C Protocol Overview
Figure 8. DS2484 Slave Address
I
2
C Interface
General Characteristics
The I
2
C bus uses a data line (SDA) and a clock signal
(SCL) for communication. Both SDA and SCL are bidi-
rectional lines connected to a positive supply voltage
through a pullup resistor. When there is no communica-
tion, both lines are high. The output stages of devices
connected to the bus must have an open drain or open
collector to perform the wired-AND function. Data on the
I
2
C bus can be transferred at rates of up to 100kbps in
standard mode and up to 400kbps in fast mode. The
DS2484 works in both modes.
A device that sends data on the bus is defined as a
transmitter, and a device receiving data is defined as a
receiver. The device that controls the communication is
called a master. The devices that are controlled by the
master are slaves. To be individually accessed, each
device must have a slave address that does not conflict
with other devices on the bus.
Data transfers can be initiated only when the bus is not
busy. The master generates the serial clock (SCL), con-
trols the bus access, generates the START and STOP
conditions, and determines the number of data bytes
transferred between START and STOP (Figure 7). Data
is transferred in bytes with the most significant bit being
transmitted first. After each byte follows an acknowledge
bit to allow synchronization between master and slave.
Slave Address
Figure 8 shows the slave address to which the DS2484
responds. The slave address is part of the slave address/
control byte. The last bit of the slave address/control
byte (R/W) defines the data direction. When set to 0,
subsequent data flows from master to slave (write access
mode); when set to 1, data flows from slave to master
(read access mode).
SDA
SCL
IDLE
1–7 89 1–7 89 1–789
START
CONDITION
STOP CONDITION
REPEATED START
SLAVE
ADDRESS
R/W ACK ACKDATA ACK/
NACK
DATA
MSB FIRST MSB LSB MSB LSB
REPEATED IF MORE BYTES
ARE TRANSFERRED
0
A6
MSB
0
A5
1
A4
1
A3
7-BIT SLAVE ADDRESS
0
A2
0
A1
0
A0
R/W
DETERMINES
READ OR WRITE