Datasheet

DS2406
30 of 32
PIO SINK CURRENT
10 mA
20 mA
30 mA
40 mA
50 mA
60 mA
70 mA
80 mA
90 mA
100 mA
I
SA
, I
SB
@ 0.4V
V
PUP
PIO-B
max.
min.
PIO-A
max.
min.
4V 5V 6V 2.8V
NOTE: The sink current is production-tested at V
PUP
= 2.8V; the specification for V
PUP
of 4V, 5V and
6V is guaranteed by design.
NOTES:
1. All voltages are referenced to ground.
2. V
PUP
, V
PUPA
, V
PUPB
= external pull-up voltage.
3. V
IH
is a function of the chip-internal supply voltage. This voltage is determined by either the external
pull-up resistor and V
PUP
or the V
CC
supply, whichever is higher. Without V
CC
supply, V
IH
for either
PIO pin should always be greater than or equal to V
PUP
-0.3V.
4. Input load is to ground.
5. Leakage current is to ground.
6. Guaranteed by design, not production tested.
7. If the current at PIO-A reaches 200mA the gate voltage of the output transistor will be reduced to
limit the sink current to 200mA. The user-supplied circuitry should limit the current flow through the
PIO-transistor to no more than 100mA. Otherwise the DS2406 may be damaged.
8. PIO-A has a controlled turn-on output. The indicated currents are DC values. At V
PUP
= 4.0V or
higher the sink current typically reaches 80% of its DC value 1 µs after turning on the transistor.
9. V
CC
must be at least 4.0V if it is to be connected during a programming pulse.
10. Capacitance on the data pin could be 800pF when power is first applied. If a 5kΩ resistor is used to
pull up the data line to V
PUP
, 5µs after power has been applied the parasite capacitance will not affect
normal communications.
11. The duration of the low pulse sent by the master should be a minimum of 2µs with a maximum value
as short as possible to allow time for the pull-up resistor to recover the line to a high level before the
1-Wire device samples in the case of a Write 1 Low Time, or before the master samples in the case of
a Read Low Time.
12. The optimal sampling point for the master is as close as possible to the end time of the 15
μs t
RDV
period without exceeding t
RDV
. For the case of a Read-one time slot, this maximizes the amount of
time for the pull-up resistor to recover the line to a high level. For a Read-zero time slot it ensures
that a read will occur before the fastest 1-Wire devices(s) release the line (t
RELEASE
= 0).