Datasheet

Datasheet 41
Pentium
®
III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
1. All signals, during their invalid states, must be guarded against spurious levels from effecting the platform
during processor power-up sequence.
2. Configuration Input signals include: A[14:5], BR0#, BR1#, INIT#. For timing of these signals, please refer to
Table 1 7 and Figure 13.
Note: For Figure 9 through Figure 15, the following apply:
1. Figure 9 through Figure 15 aretobeusedinconjunctionwithTable 14 through Table 20.
2. All AC timings for the AGTL+ signals at the processor pins are referenced to the BCLK rising
edge at 1.25 V. All AGTL+ signal timings (address bus, data bus, etc.) are referenced at 1.00 V
at the processor pins.
3. All AC timings for the APIC I/O signals at the processor pins are referenced to the PICCLK
rising edge at 1.25 V. All APIC I/O signal timings are referenced at 0.75 V at the processor
pins.
4. All AC timings for the TAP signals at the processor pins are referenced to the TCK rising edge
at 0.75 V. All TAP signal timings (TMS, TDI, etc.) are referenced at 0.75 V at the processor
pins.
Figure 9. Generic Clock Waveform
Vih
BCLK#
BCLK
Vil
Vcross
Tp
Tp = T1 (BCLK Period)
NOTE: Single-Ended clock uses BCLK only,
Differential clock uses BLCK and BCLK#