Datasheet

ManualsBrandsFairchild ManualsDiscrete SemiconductorsMOSFET N, 25 V 0.68 A 350 mW SOT-23

August 1997

FDV303N

Digital FET, N-Channel

General Description Features

Absolute Maximum Ratings T

= 25

C unless other wise noted

Symbol Parameter FDV303N Units

DSS

Drain-Source Voltage, Power Supply Voltage 25 V

GSS

Gate-Source Voltage, V

8 V

Drain/Output Current - Continuous 0.68 A

- Pulsed 2

Maximum Power Dissipation 0.35 W

STG

Operating and Storage Temperature Range -55 to 150 °C

ESD Electrostatic Discharge Rating MIL-STD-883D

Human Body Model (100pf / 1500 Ohm)

6.0 kV

THERMAL CHARACTERISTICS

Thermal Resistance, Junction-to-Ambient 357 °C/W

FDV303N Rev.D1

25 V, 0.68 A continuous, 2 A Peak.

DS(ON)

= 0.45 Ω @ V

= 4.5 V

DS(ON)

= 0.6 Ω @ V

= 2.7 V.

Very low level gate drive requirements allowing direct

operation in 3V circuits. V

GS(th)

< 1.5V.

Gate-Source Zener for ESD ruggedness.

>6kV Human Body Model

Compact industry standard SOT-23 surface mount

package.

Alternative to TN0200T and TN0201T.

These N-Channel enhancement mode field effect transistors are

produced using Fairchild's proprietary, high cell density, DMOS

technology. This very high density process is tailored to minimize

on-state resistance at low gate drive conditions. This device is

designed especially for application in battery circuits using either

one lithium or three cadmium or NMH cells. It can be used as an

inverter or for high-efficiency miniature discrete DC/DC

conversion in compact portable electronic devices like cellular

phones and pagers. This device has excellent on-state

resistance even at gate drive voltages as low as 2.5 volts.

Mark:303

SOT-23

SuperSOT

-8

SOIC-16

SO-8

SOT-223

SuperSOT

-6

Summary of content (4 pages)

PAGE 1
August 1997 FDV303N Digital FET, N-Channel General Description Features These N-Channel enhancement mode field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is tailored to minimize on-state resistance at low gate drive conditions. This device is designed especially for application in battery circuits using either one lithium or three cadmium or NMH cells.
PAGE 2
Electrical Characteristics (TA = 25 OC unless otherwise noted ) Symbol Parameter Conditions Min Typ Max Units OFF CHARACTERISTICS BVDSS Drain-Source Breakdown Voltage VGS = 0 V, ID = 250 µA ∆BVDSS/∆TJ Breakdown Voltage Temp.
PAGE 3
Typical Electrical Characteristics 2 VGS = 4.5V 3.5 3.0 2.7 1.2 2.5 R DS(on) , NORMALIZED DRAIN-SOURCE ON-RESISTANCE I D , DRAIN-SOURCE CURRENT (A) 1.5 2.0 0.9 0.6 1.5 0.3 0 VGS = 2.0V 1.5 2.7 0.5 1 1.5 3.5 4.5 2 0 0.2 0.6 0.8 1 1.2 Figure 2. On-Resistance Variation with Drain Current and Gate Voltage. Figure 1. On-Region Characteristics. 1.6 2 ID= 0.5A I D =0.5 A VGS = 4.5 V 1.4 R DS(on) , ON-RESISTANCE (OHM) R DS(ON), NORMALIZED 0.
PAGE 4
Typical Electrical And Thermal Characteristics 5 V GS , GATE-SOURCE VOLTAGE (V) 150 VDS = 5V I D = 0.5A 100 10V 4 CAPACITANCE (pF) 15V 3 2 Ciss 50 Coss 20 10 f = 1 MHz V GS = 0V C rss 1 0 5 0.1 0 0.4 0.8 1.2 1.6 0.5 2 V DS 1 2 5 10 25 , DRAIN TO SOURCE VOLTAGE (V) Q g , GATE CHARGE (nC) Figure 8. Capacitance Characteristics. Figure 7. Gate Charge Characteristics. 5 5 1m s 10m s 10 0.3 0m s 1s 10 0.1 0.01 0.1 0.2 0.5 s 3 2 DC V GS = 4.