User Manual

ManualsBrandsDigilent ManualsDevelopment Boards & KitsDigital Discovery Logic Analyser + High Speed Adapter and Probe Bundle

The Digilent Digital Discovery™ is a combined logic analyzer and pattern generator instrument that was created to be the ultimate

embedded development companion. The Digital Discovery was designed to optimize channels, speed, and portability. The small form

factor facilitates easy storage and provides a whole suite of advanced features to allow you to debug, visualize, and stimulate digital signals

for most embedded projects. The digital inputs and outputs can be connected to a circuit using simple wire probes or breadboard wires;

alternatively, the Digital Discovery High Speed Adapter and impedance-matched probes can be used to connect and utilize the inputs and

outputs for more advanced projects. The Digital Discovery is driven by the free

WaveForms

(https://reference.digilentinc.com/reference/software/waveforms/waveforms-3/start) (3.5.4 or later) software and can be configured to be any

of the instruments below:

24-channel digital logic analyzer (1.2…3.3V CMOS, up to 800MS/s(with the High Speed Adapter))

16-channel pattern generator (1.2…3.3V CMOS, 100MS/s)

16-channel virtual digital I/O including buttons, switches, and LEDs – perfect for logic training applications

A programmable power supply of 1.2…3.3V/100mA. The same voltage supplies the Logic Analyzer input buffers and the Pattern

Generator input/output buffers, for keeping the logic level compatibility with the circuit under test.

Digital Bus Analyzers (SPI, I²C, UART, I2S, CAN, Parallel)

The Digital Discovery was designed for anyone embarking on embedded development. Its features and specifications were deliberately

chosen to maintain a small and portable form factor, withstand use in a variety of environments, and keep costs down, while balancing

the requirements of operating on USB Power.

Digital Discovery Reference Manual



Summary of content (19 pages)

PAGE 1
Digital Discovery Reference Manual The Digilent Digital Discovery™ is a combined logic analyzer and pattern generator instrument that was created to be the ultimate embedded development companion. The Digital Discovery was designed to optimize channels, speed, and portability. The small form factor facilitates easy storage and provides a whole suite of advanced features to allow you to debug, visualize, and stimulate digital signals for most embedded projects.
PAGE 2
PAGE 3
PAGE 4
PAGE 5
PAGE 6
1.1 Architectural Overview and Block Diagram Digital Discovery's high-level block diagram is presented in Figure 2, below. The core of the Digital Discovery 2 is the Xilinx® Spartan®-6 FPGA (specifically, the XC6SLX25-2 device). The WaveForms application automatically programs the Discovery’s FPGA at start-up with a configuration file designed to implement a multi-function test and measurement instrument.
PAGE 7
The I/O Level Translators build the bidirectional interface for input/output pins (used in the Pattern Generator, Static IO, and Logic Analyzer) The Input Dividers are the conditioning circuits for the input pins (used in the Logic Analyzer) The FPGA banks are supplied at different voltages: Bank 0, Bank1: VCCIO_PROG, a variable voltage, settable in the range 1.2V…3.3V. The logic standard is set to: LVCMOS18_JEDEC. The threshold voltage is about 0.45*VCCIO_PROG. Bank 2: VCC3V3, a fixed voltage of 3.3V.
PAGE 8
Figure 4. I/O level translator. [] The LDO in Figure 5 generates the 4.3V to supply the level translator in Figure 4. The charge-pump in Figure 6 provides the the 6V reference for the clipper in Figure 7. When all ESD diodes protecting DIO_USR in Figure 3 are OFF, Q3B is OFF, and also Q4. If overvoltage is applied on some DIO_USR pins, rising VU5V2_ESD in Figure 7 above 5.2V, Q3B and Q4 turn ON , clipping VU5V2_ESD at approximately 5V. Figure 5. VCCIO_SW supply. [] Figure 6. VU6V0 supply.
PAGE 9
Figure Figure 7. Backpowering voltage clipper. [] 3. Input Dividers Figure 8 shows the DIN user connector and Figure 9 shows the Input Divider for DIN0. DIN1 to DIN23 use similar input circuitry. The Input Dividers block includes: Frequency compensated voltage dividers: 10/11 resistive dividers with compensation for FPGA input capacitance. All the dividers together have the settable reference voltage VREFIO.
PAGE 10
Figure 10 VREFIO reference. [] 4. Power supplies and control 4.1 Internal power supplies In Figure 11, IC16 limits the in-rush current when the device is connected to the USB port. INA214 is a current shunt amplifier, with a gain of 100. With Vref = 0.75V and R163 = 15mΩ, the output voltage is: VI SN S_V BU S = 100 ∙ (VI N + − VI N − ) + 0.75V = 1.5 ∙ IV U 5V 0 + 0.75V (2) The VBUS voltage is halved to VSNS_VBUS, for being also monitored.
PAGE 11
Figure 12. Internal voltage supplies. [] 4.2 Programmable power supply IC13 in Figure 13 generates the VCCIO_PROG, the variable voltage to supply the input and IO banks of the FPGA: VV CCI O_P ROG = VF B ∙ (1 + R144 R146 + R144 R149 ) − VV SET _V CCI O ∙ R144 R146 = 3.42V − VV SET _V CCI O ∙ 0.82 (3) With VVSET_VCCIO ϵ (0…3V), VCCIO_PROG could be theoretically set in the range: VCCIO_PROG ϵ (1.02V…3.42V). IC15 is a current shunt amplifier, with a gain of 100. With Vref = 0.
PAGE 12
Figure 14. VCCIO_USR protection and switch. [] 4.3. Monitoring the power supplies The microcontroller in Figure 15 has two roles: 1. A/D () Conversion of VVSNS_VBUS, VISNS_VBUS, VVSNS_USR, VISNS_USR, representing the voltages and currents consumed from VBUS and VCCIO_USR respectively. The digital results are passed to the FPGA via an SPI interface. 2. Storing the calibration parameters computed as a part of the manufacturing test.
PAGE 13
Figure 16. VSET_VCCIO setting DAC. [] Figure 17. VREF3V0 . [] 5. LEDs and DDR3 Memory Figure 18 shows the two tricolor LEDs used to symbolize the Digital discovery status. Figure 19 shows the DDR3 memory for the Logic Analyzer buffer. Figure 18. LEDs.
PAGE 14
Figure 19. DDR3 memory. [] 6. USB Controller The USB interface performs two tasks: Programming the FPGA: There is no non-volatile FPGA configuration memory on the Digital Discovery. The WaveForms software identifies the connected device and downloads an appropriate .bit file at power-up, via a Digilent USB-JTAG interface. Adept run-time is used for low level protocols.
PAGE 15
Detail of the trigger system is shown in Figure 20. Each instrument generates a trigger signal when a trigger condition is met. Each trigger signal (including external triggers) can trigger any instrument and drive the external trigger outputs. This way, all the instruments can synchronize to each other. Figure 20. FPGA configuration trigger block diagram. [] Figure 21 shows the connections to the FPGA banks 0, 1 and 3. Bank 0 is used for IOs.
PAGE 16
Figure 21. FPGA banks 0, 1 and 3. [] Figure 22 shows the voltage rails and decoupling for the FPGA. The internal core of the FPGA is supplied 1.2V. Banks 0 and 1 are supplied with the programmable VCCIO_PROG. By setting this from 1.2V to 3.3V, both inputs and IOs are set to be compatible with the I/O standard LVCMOS of the respective voltage. Notice that a protected version of VCCIO_PROG is also available to the user, as VCCIO_USR. This can be used to supply the Device/Circuit Under Test.
PAGE 17
Figure 22. FPGA powering and decoupling. [] 8. Accessories The Digital Discovery package includes; One 2×16 fly-wire assembly (datasheet (https://reference.digilentinc.com/_media/reference/instrumentation/digital-discovery/250096_sn-1050323-1.pdf)), for the DIN_USR connector. 24DIN signals (various colors), 8 GND () wires (black). The connector is keyed so that the correct pins are connected to the correct color wires. One 2×6 fly-wire assembly (datasheet (https://reference.digilentinc.
PAGE 18
High Speed Logic Probes (datasheet (https://reference.digilentinc.com/_media/reference/instrumentation/digital-discovery/250104_dp_2.54_3.pdf)). Each twisted cable has a GND () (black) wire twisted to a DIN_USR (colored) wire. The wire connects to the High Speed Adapter via a 2 pin female header, and two 1 pin female connectors to the device under test. A 100Ω resistor is embedded in the signal wire, on the end closest to the device under test.
PAGE 19
signal is read at the FPGA pin and does not propagate through the external DIO circuitry. Consequently, when combining DIN and DIO pins in the Logic Analyzer, misalignments can be observed, at high acquisition rate. 2) Available combinations in WaveForms: - 200MHz, DIN0…23, DIO24…31 - 200MHz, DIO24…39, DIN0…15 - 400MHz, DIN0… 15 - 400MHz, DIO24…39 - 800MHz, DIN0…7 - 800MHz, DIO24…31 3) The FPGA DIN and DIO pins are set to LVCMOS18_JEDEC IOSTANDARD.