Datasheet

ADV7189B
Rev. B | Page 22 of 104
AD_N443_EN Enable Autodetection of NTSC 443,
Address 0x07[5]
Setting AD_N443_EN to 0 disables the autodetection of NTSC
style systems with a 4.43 MHz color subcarrier.
Setting AD_N443_EN to 1 (default) enables the detection.
AD_P60_EN Enable Autodetection of PAL60,
Address 0x07[4]
Setting AD_P60_EN to 0 disables the autodetection of PAL
systems with a 60 Hz field rate.
Setting AD_P60_EN to 1 (default) enables the detection.
AD_PALN_EN Enable Autodetection of PAL N,
Address 0x07[3]
Setting AD_PALN_EN to 0 disables the detection of the
PAL N standard.
Setting AD_PALN_EN to 1 (default) enables the detection.
AD_PALM_EN Enable Autodetection of PAL M,
Address 0x07[2]
Setting AD_PALM_EN to 0 disables the autodetection of PAL M.
Setting AD_PALM_EN to 1 (default), enables the detection.
AD_NTSC_EN Enable Autodetection of NTSC,
Address 0x07[1]
Setting AD_NTSC_EN to 0 disables the detection of standard
NTSC.
Setting AD_NTSC_EN to 1 (default) enables the detection.
AD_PAL_EN Enable Autodetection of PAL,
Address 0x07[0]
Setting AD_PAL_EN to 0 disables the detection of standard PAL.
Setting AD_PAL_EN to 1 (default) enables the detection.
SFL_INV Subcarrier Frequency Lock Inversion
This bit controls the behavior of the PAL switch bit in the SFL
(GenLock Telegram) data stream. It was implemented to solve
some compatibility issues with video encoders. It solves two
problems as follows:
First, the PAL switch bit is only meaningful in PAL. Some
encoders (including Analog Devices encoders) also look at the
state of this bit in NTSC.
Second, there was a design change in Analog Devices encoders
from ADV717x to ADV719x. The older versions used the SFL
(GenLock Telegram) bit directly, while the later ones invert the
bit prior to using it. The reason for this is the inversion
compensated for the 1-line delay of an SFL (GenLock Telegram)
transmission.
As a result, ADV717x encoders need the PAL switch bit in the
SFL (GenLock Telegram) to be 1 for NTSC to work. Also,
ADV7190/ADV7191/ADV7194 encoders need the PAL switch
bit in the SFL to be 0 to work in NTSC. If the state of the PAL
switch bit is wrong, a 180° phase shift occurs.
In a decoder/encoder back-to-back system in which SFL is used,
this bit must be set up properly for the specific encoder used.
SFL_INV Address 0x41[6]
Setting SFL_INV[6] to 0 makes the part SFL-compatible with
ADV7190/ADV7191/ADV7194 encoders.
Setting SFL_INV to 1 (default) makes the part SFL-compatible
with ADV717x/ADV7173x encoders.
Lock-Related Controls
Lock information is presented to the user through Bits[1:0] of
the Status 1 register. See the
169HSTATUS_1[7:0] Address 0x10[7:0]
section.
170HFigure 9 outlines the signal flow and the controls avail-
able to influence the way the lock status information is generated.
04983-0-009
1
0
TIME_WIN
FREE_RUN
STATUS 1 [0]
SELECT THE RAW LOCK SIGNAL
SRLS
FILTER THE RAW LOCK SIGNAL
CIL[2:0], COL[2:0]
TAKE F
SC
LOCK INTO ACCOUNT
FSCLE
STATUS 1 [1]
F
SC
LOCK
1
0
COUNTER INTO LOCK
COUNTER OUT OF LOCK
MEMORY
Figure 9. Lock-Related Signal Path