Datasheet

ADF4107 Data Sheet
Rev. D | Page 4 of 20
Parameter B Version
1
B Chips
2
(Typ) Unit Test Conditions/Comments
Phase Noise Performance
12
@ VCO output
900 MHz Output
13
−93 −93 dBc/Hz typ @ 1 kHz offset and 200 kHz PFD frequency
6400 MHz Output
14
−76 −76 dBc/Hz typ @ 1 kHz offset and 200 kHz PFD frequency
6400 MHz Output
15
−83 −83 dBc/Hz typ @ 1 kHz offset and 1 MHz PFD frequency
Spurious Signals
900 MHz Output
13
−90/−92 −90/−92 dBc typ
@ 200 kHz/400 kHz and 200 kHz PFD
frequency
6400 MHz Output
14
−65/−70 −65/−70 dBc typ
@ 200 kHz/400 kHz and 200 kHz PFD
frequency
6400 MHz Output
15
−70/−75 −70/−75 dBc typ @ 1 MHz/2 MHz and 1 MHz PFD frequency
1
Operating temperature range (B version) is −40°C to +85°C.
2
The B chip specifications are given as typical values.
3
Use a square wave for lower frequencies, below the minimum stated.
4
This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency that
is less than this value.
5
AV
DD
= DV
DD
= 3 V.
6
AC-coupling ensures AV
DD
/2 bias.
7
Guaranteed by design. Sample tested to ensure compliance.
8
T
A
= 25°C; AV
DD
= DV
DD
= 3 V; P = 32; RF
IN
= 7.0 GHz.
9
T
A
= 25°C; AV
DD
= DV
DD
= 3.3 V; R = 16,383; A = 63; B = 891; P = 32; RF
IN
= 7.0 GHz.
10
The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20logN (where N is the N divider value)
and 10 log(F
PFD
). PN
SYNTH
= PN
TOT
– 20 logN −10 logF
PFD
.
11
The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency, f
RF
,
and at a frequency offset, f, is given by PN = PN
1_f
+ 10 log(10 kHz/f) + 20 log(f
RF
/1 GHz). Both the normalized phase noise floor and flicker noise are modeled in
ADIsimPLL.
12
The phase noise is measured with the EV-ADF411xSD1Z evaluation board and the HP8562E spectrum analyzer. The spectrum analyzer provides the REF
IN
for the
synthesizer (f
REFOUT
= 10 MHz @ 0 dBm).
13
f
REFIN
= 10 MHz; f
PFD
= 200 kHz; offset frequency = 1 kHz; f
RF
= 900 MHz; N = 4500; loop BW = 20 kHz.
14
f
REFIN
= 10 MHz; f
PFD
= 200 kHz; offset frequency = 1 kHz; f
RF
= 6400 MHz; N = 32,000; loop BW = 20 kHz.
15
f
REFIN
= 10 MHz; f
PFD
= 1 MHz; offset frequency = 1 kHz; f
RF
= 6400 MHz; N = 6400; loop BW = 100 kHz.
TIMING CHARACTERISTICS
AV
DD
= DV
DD
= 3 V ± 10%, AV
DD
≤ V
P
≤ 5.5 V, AGND = DGND = CPGND = 0 V, R
SET
= 5.1 kΩ, dBm referred to 50 Ω, T
A
= T
MAX
to T
MIN
,
unless otherwise noted.
1
Table 2.
Parameter Limit
2
(B Version) Unit Test Conditions/Comments
t
1
10 ns min DATA to CLOCK setup time
t
2
10 ns min DATA to CLOCK hold time
t
3
25 ns min CLOCK high duration
t
4
25 ns min CLOCK low duration
t
5
10 ns min CLOCK to LE setup time
t
6
20 ns min LE pulse width
1
Guaranteed by design but not production tested.
2
Operating temperature range (B Version) is −40°C to +85°C.
03338-002
CLOCK
DB22
DB2
DATA
LE
t
1
LE
DB23 (MSB)
t
2
DB1 (CONTROL
BIT C2)
DB0 (LSB)
(CONTROL BIT C1)
t
3
t
4
t
6
t
5
Figure 2. Timing Diagram