2-Channel, 500 MSPS DDS with 10-Bit DACs AD9958 Data Sheet FEATURES APPLICATIONS 2 synchronized DDS channels @ 500 MSPS Independent frequency/phase/amplitude control between channels Matched latencies for frequency/phase/amplitude changes Excellent channel-to-channel isolation (>72 dB) Linear frequency/phase/amplitude sweeping capability Up to 16 levels of frequency/phase/amplitude modulation (pin-selectable) 2 integrated 10-bit digital-to-analog converters (DACs) Individually programmable DAC full-scale
AD9958 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Linear Sweep Mode .................................................................... 26 Applications ....................................................................................... 1 Linear Sweep No-Dwell Mode ................................................. 27 Functional Block Diagram ..............................................................
Data Sheet AD9958 GENERAL DESCRIPTION The DAC outputs are supply referenced and must be terminated into AVDD by a resistor or an AVDD center-tapped transformer. Each DAC has its own programmable reference to enable different full-scale currents for each channel. The AD9958 consists of two DDS cores that provide independent frequency, phase, and amplitude control on each channel.
AD9958 Data Sheet SPECIFICATIONS AVDD and DVDD = 1.8 V ± 5%; DVDD_I/O = 3.3 V ± 5%; T = 25°C; RSET = 1.91 kΩ; external reference clock frequency = 500 MSPS (REFCLK multiplier bypassed), unless otherwise noted. Table 1.
Data Sheet Parameter 75.1 MHz Analog Output (±50 kHz) 75.1 MHz Analog Output (±250 kHz) 75.1 MHz Analog Output (±1 MHz) 100.3 MHz Analog Output (±10 kHz) 100.3 MHz Analog Output (±50 kHz) 100.3 MHz Analog Output (±250 kHz) 100.3 MHz Analog Output (±1 MHz) 200.3 MHz Analog Output (±10 kHz) 200.3 MHz Analog Output (±50 kHz) 200.3 MHz Analog Output (±250 kHz) 200.3 MHz Analog Output (±1 MHz) PHASE NOISE CHARACTERISTICS Residual Phase Noise @ 15.
AD9958 Parameter Residual Phase Noise @ 15.1 MHz (fOUT) with REFCLK Multiplier Enabled 20× @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset @ 1 MHz Offset Residual Phase Noise @ 40.1 MHz (fOUT) with REFCLK Multiplier Enabled 20× @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset @ 1 MHz Offset Residual Phase Noise @ 75.1 MHz (fOUT) with REFCLK Multiplier Enabled 20× @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset @ 1 MHz Offset Residual Phase Noise @ 100.
Data Sheet Parameter POWER SUPPLY Total Power Dissipation—Both Channels On, SingleTone Mode Total Power Dissipation—Both Channels On, with Sweep Accumulator Total Power Dissipation—Full Power-Down IAVDD—Both Channels On, Single-Tone Mode IAVDD—Both Channels On, Sweep Accumulator, REFCLK Multiplier, and 10-Bit Output Scalar Enabled IDVDD—Both Channels On, Single-Tone Mode IDVDD—Both Channels On, Sweep Accumulator, REFCLK Multiplier, and 10-Bit Output Scalar Enabled IDVDD_I/O IAVDD Power-Down Mode IDVDD Power
AD9958 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Maximum Junction Temperature DVDD_I/O (Pin 49) AVDD, DVDD Digital Input Voltage (DVDD_I/O = 3.3 V) Digital Output Current Storage Temperature Range Operating Temperature Range Lead Temperature (10 sec Soldering) θJA θJC Rating 150°C 4V 2V −0.7 V to +4 V 5 mA –65°C to +150°C –40°C to +85°C 300°C 21°C/W 2°C/W Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device.
Data Sheet AD9958 56 55 54 53 52 51 50 49 48 47 46 45 44 43 DGND DVDD SYNC_CLK SDIO_3 SDIO_2 SDIO_1 SDIO_0 DVDD_I/O SCLK CS I/O_UPDATE DVDD DGND P3 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PIN 1 INDICATOR AD9958 TOP VIEW (Not to Scale) 42 41 40 39 38 37 36 35 34 33 32 31 30 29 P2 P1 P0 AVDD NC AVDD AVDD AVDD NC AVDD NC AVDD AVDD AVDD NOTES 1. THE EXPOSED EPAD ON BOTTOM SIDE OF PACKAGE IS AN ELECTRICAL CONNECTION AND MUST BE SOLDERED TO GROUND. 2.
AD9958 Data Sheet Pin No. 24 Mnemonic CLK_MODE_SEL I/O 1 I 27 LOOP_FILTER I 28, 32, 34, 38 40, 41, 42, 43 NC P0, P1, P2, P3 N/A I 46 I/O_UPDATE I 47 48 CS SCLK I I 49 50 51, 52, 53 DVDD_I/O SDIO_0 SDIO_1, SDIO_2, SDIO_3 I I/O I/O 54 SYNC_CLK O 1 Description Control Pin for the Oscillator Section. Caution: Do not drive this pin beyond 1.8 V. When high (1.8 V), the oscillator section is enabled to accept a crystal as the REF_CLK source. When low, the oscillator section is bypassed.
Data Sheet AD9958 TYPICAL PERFORMANCE CHARACTERISTICS DELTA 1 (T1) –71.73dB 4.50901804MHz REF LVL 0dBm RBW VBW SWT 20kHz 20kHz 1.6s RF ATT 20dB UNIT dB REF LVL 0dBm 0 0 A –30 –40 –40 –50 RF ATT 20dB UNIT dB A 1 1AP –50 –60 –60 –70 –70 –80 –80 05252-006 START 0Hz 25MHz/DIV STOP 250MHz –100 START 0Hz DELTA 1 (T1) –62.84dB 40.08016032MHz RBW VBW SWT 20kHz 20kHz 1.6s RF ATT 20dB UNIT dB STOP 250MHz 25MHz/DIV Figure 7. Wideband SFDR, fOUT = 15.
AD9958 REF LVL 0dBm Data Sheet DELTA 1 (T1) –84.73dB 254.50901604kHz 0 RBW VBW SWT 500Hz 500Hz 20s RF ATT 20dB UNIT dB REF LVL 0dBm 1 dB A –20 1AP –30 –40 –40 (dB) –50 –50 –60 –60 –70 –70 –80 –80 –90 1AP CENTER 1.1MHz SPAN 1MHz 100kHz/DIV CENTER 15.1MHz Figure 10. NBSFDR, fOUT = 1.1 MHz, fCLK = 500 MSPS, ±1 MHz REF LVL 0dBm RBW VBW SWT DELTA 1 (T1) –84.10dB 120.24048096kHz 0 500Hz 500Hz 20s RF ATT 20dB UNIT dB 100kHz/DIV SPAN 1MHz Figure 13. NBSFDR, fOUT = 15.
Data Sheet AD9958 –100 –60 75.1MHz CHANNEL ISOLATION (dBc) PHASE NOISE (dBc/Hz) –110 –120 –130 100.3MHz –140 –150 40.1MHz –65 –70 SINGLE DAC POWER PLANE –75 –80 –160 15.1MHz –85 100 1k 10k 100k 1M 10M 05252-018 10 FREQUENCY OFFSET (Hz) Figure 16. Residual Phase Noise (SSB) with fOUT = 15.1 MHz, 40.1MHz, 75.1 MHz, 100.3 MHz; fCLK = 500 MHz with REFCLK Multiplier Bypassed 25.3 50.3 75.3 100.3 125.3 150.3 175.3 200.
AD9958 Data Sheet APPLICATION CIRCUITS PULSE ANTENNA RADIATING ELEMENTS AD9958 CH0 FILTER FILTER CH1 FILTER FILTER 05252-024 LO REFCLK Figure 22. Phase Array Radar Using Precision Frequency/Phase Control from DDS in FMCW or Pulsed Radar Applications; DDS Provides Either Continuous Wave or Frequency Sweep AD8348 AD8347 AD8346 ADL5390 I BASEBAND AD8349 CH0 LO AD9958 PHASE SPLITTER RF OUTPUT CH1 05252-025 REFCLK Q BASEBAND Figure 23.
Data Sheet AD9958 AD9510 CLOCK DISTRIBUTOR WITH DELAY EQUALIZATION CLOCK SOURCE REF_CLK AD9510 SYNCHRONIZATION DELAY EQUALIZATION SYNC_OUT C1 S1 SYNC_IN DATA AD9958 FPGA A1 (MASTER) SYNC_CLK C2 S2 DATA AD9958 FPGA SYNC_CLK CENTRAL CONTROL A2 (SLAVE 1) C3 S3 DATA AD9958 FPGA A3 (SLAVE 2) SYNC_CLK AD9958 A4 (SLAVE 3) SYNC_CLK A_END 05252-027 C4 S4 DATA FPGA Figure 25.
AD9958 Data Sheet PROGRAMMABLE 1 TO 32 DIVIDER AND DELAY ADJUST CLOCK OUTPUT SELECTION(S) AD9515 AD9514 AD9513 AD9512 CH0 n LVPECL LVDS CMOS n LVPECL LVDS CMOS CH1 IMAGE AD9515 AD9514 AD9513 AD9512 n = DEPENDENT ON PRODUCT SELECTION 05252-030 AD9958 REFCLK Figure 28. Clock Generation Circuit Using the AD9512/AD9513/AD9514/AD9515 Series of Clock Distribution Chips Rev.
Data Sheet AD9958 EQUIVALENT INPUT AND OUTPUT CIRCUITS DVDD_I/O = 3.3V INPUT OUTPUT 05252-102 AVOID OVERDRIVING DIGITAL INPUTS. FORWARD BIASING DIODES MAY COUPLE DIGITAL NOISE ON POWER PINS. Figure 29. CMOS Digital Inputs TERMINATE OUTPUTS INTO AVDD. DO NOT EXCEED VOLTAGE COMPLIANCE OF OUTPUTS. 05252-132 CHx_IOUT CHx_IOUT Figure 30. DAC Outputs AVDD 1.5kΩ Z Z 1.5kΩ REF_CLK AVDD AVDD OSC AMP REF_CLK INPUTS ARE INTERNALLY BIASED AND NEED TO BE AC-COUPLED. OSC INPUTS ARE DC-COUPLED.
AD9958 Data Sheet THEORY OF OPERATION DDS CORE DIGITAL-TO-ANALOG CONVERTER The AD9958 has two DDS cores, each consisting of a 32-bit phase accumulator and phase-to-amplitude converter. Together, these digital blocks generate a digital sine wave when the phase accumulator is clocked and the phase increment value (frequency tuning word) is greater than 0. The phase-to-amplitude converter simultaneously translates phase information to amplitude information by a cos(θ) operation.
Data Sheet AD9958 MODES OF OPERATION There are many combinations of modes (for example, singletone, modulation, linear sweep) that the AD9958 can perform simultaneously. However, some modes require multiple data pins, which can impose limitations. The following guidelines can help determine if a specific combination of modes can be performed simultaneously by the AD9958.
AD9958 Data Sheet REFERENCE CLOCK MODES The AD9958 supports multiple reference clock configurations to generate the internal system clock. As an alternative to clocking the part directly with a high frequency clock source, the system clock can be generated using the internal, PLL-based reference clock multiplier. An on-chip oscillator circuit is also available for providing a low frequency reference signal by connecting a crystal to the clock input pins.
Data Sheet AD9958 39pF 25MHz XTAL When FR1[6] = 1 and the PWR_DWN_CTL input pin is high, the AD9958 is put into full power-down mode. In this mode, all functions are powered down. This includes the DAC and PLL, which take a significant amount of time to power up. When the PLL is bypassed, the PLL is shut down to conserve power. REF_CLK PIN 23 05252-119 REF_CLK PIN 22 39pF Figure 35. Crystal Input Configuration SCALABLE DAC REFERENCE CURRENT CONTROL MODE RSET is common to all four DACs.
AD9958 Data Sheet In modulation mode, the amplitude frequency phase (AFP) select bits (CFR[23:22]) and modulation level bits (FR1[9:8]) are programmed to configure the modulation type and level (see Table 6 and Table 7). Note that the linear sweep enable bit must be set to Logic 0 in direct modulation mode. If the profile pins are used for RU/RD, Logic 0 is for ramp-up and Logic 1 is for ramp-down.
Data Sheet AD9958 Eight-Level Modulation—No RU/RD For the conditions in Table 12, the profile register chosen is based on the 4-bit value presented to Profile Pins [P0:P3]. For example, if PPC = X11 and [P0:P3] = 1110, the contents of the Channel Word 14 register of Channel 1 is presented to the output of Channel 1. The modulation level bits (FR1[9:8]) are set to 10 (eight-level). The AFP select bits (CFR[23:22]) are set to a nonzero value.
AD9958 Data Sheet MODULATION USING SDIO_x PINS FOR RU/RD For RU/RD bits = 11, the SDIO_1, SDIO_2, and SDIO_3 pins are available for RU/RD. In this mode, modulation levels of 2, 4, and 16 are available. Note that the serial I/O port can be used only in 1-bit serial mode. Two-Level Modulation Using SDIO Pins for RU/RD Table 15. Profile Pin and Channel Assignments in Two-Level Modulation (RU/RD Enabled) Profile Pin Config.
Data Sheet AD9958 Setting the Slope of the Linear Sweep Linear sweep mode enables the user to sweep frequency, phase, or amplitude from a starting point (S0) to an endpoint (E0). The purpose of linear sweep mode is to provide better bandwidth containment compared to direct modulation by replacing greater instantaneous changes with more gradual, user-defined changes between S0 and E0.
AD9958 Data Sheet This load and countdown operation continues for as long as the timer is enabled. However, the count can be reloaded before reaching 1 by either of the following two methods: When the profile pin transitions from high to low, the FDW is applied to the input of the sweep accumulator and the FSRR bits are loaded into the sweep rate timer. The FDW accumulates at the rate given by the falling sweep ramp rate (FSRR) until the output is equal to the CFTW0 register (Register 0x04) value.
Data Sheet AD9958 fOUT B B B FTW1 A FTW0 A A TIME SINGLE-TONE MODE P2 = 1 P2 = 0 P2 = 1 P2 = 0 P2 = 1 05252-147 P2 = 0 LINEAR SWEEP MODE ENABLE—NO-DWELL BIT SET Figure 38. Channel 0 in Linear Sweep Mode (No-Dwell Enabled) fOUT B FTW1 A FTW0 TIME P2 = 0 LINEAR SWEEP MODE P2 = 1 P2 = 0 AT POINT A: LOAD RISING RAMP RATE REGISTER, APPLY RDW<31:0> AT POINT B: LOAD FALLING RAMP RATE REGISTER, APPLY FDW<31:0> 05252-148 SINGLE-TONE MODE Figure 39.
AD9958 Data Sheet OUTPUT AMPLITUDE CONTROL MODE A special feature of this mode is that the maximum output amplitude allowed is limited by the contents of the amplitude scale factor (ACR[9:0]). This allows the user to ramp to a value less than full scale. The 10-bit scale factor (multiplier) controls the ramp-up and ramp-down (RU/RD) time of an on/off emission from the DAC. In burst transmissions of digital data, it reduces the adverse spectral impact of abrupt bursts of data.
Data Sheet AD9958 SYNCHRONIZING MULTIPLE AD9958 DEVICES The AD9958 allows easy synchronization of multiple AD9958 devices. At power-up, the phase of SYNC_CLK can be offset between multiple devices. To correct for the offset and align the SYNC_CLK edges, there are three methods (one automatic mode and two manual modes) of synchronizing the SYNC_CLK edges. These modes force the internal state machines of multiple devices to a known state, which aligns the SYNC_CLK edges.
AD9958 Data Sheet If the setup time between these signals is met, then constant latency (pipeline) to the DAC output exists. For example, if repetitive changes to phase offset via the SPI port is desired, the latency of those changes to the DAC output is constant; otherwise, a time uncertainty of one SYNC_CLK period is present. I/O_UPDATE, SYNC_CLK, AND SYSTEM CLOCK RELATIONSHIPS I/O_UPDATE and SYNC_CLK are used together to transfer data from the serial I/O buffer to the active registers in the device.
Data Sheet AD9958 SERIAL I/O PORT Three of the four data pins (SDIO_1, SDIO_2, SDIO_3) can be used for functions other than serial I/O port operation. These pins can also be used to initiate a ramp-up or ramp-down (RU/RD) of the 10-bit amplitude output scalar. In addition, SDIO_3 can be used to provide the SYNC_I/O function that resynchronizes the serial I/O port controller if it is out of proper sequence.
AD9958 Data Sheet Each set of communication cycles does not require an I/O update to be issued. The I/O update transfers data from the I/O port buffer to active registers. The I/O update can be sent for each communication cycle or can be sent when all serial operations are complete. However, data is not active until an I/O update is sent, with the exception of the channel enable bits in the channel select register (CSR). These bits do not require an I/O update to be enabled.
Data Sheet AD9958 SERIAL I/O MODES OF OPERATION The following are the four programmable modes of serial I/O port operation: • • • • Single-bit serial 2-wire mode (default mode) Single-bit serial 3-wire mode 2-bit serial mode 4-bit serial mode (SYNC_I/O not available) Table 26 displays the function of all six serial I/O interface pins, depending on the mode of serial I/O operation programmed. Table 26. Serial I/O Port Pin Function vs.
AD9958 Data Sheet DATA TRANSFER CYCLE INSTRUCTION CYCLE CS I5 (I2) I6 (I1) D7 (D0) I0 (I7) I1 (I6) I2 (I5) I3 (I4) I4 (I3) D6 (D1) D4 (D3) D5 (D2) D3 (D4) D2 (D5) Figure 43. Single-Bit Serial Mode Write Timing—Clock Stall Low INSTRUCTION CYCLE DATA TRANSFER CYCLE CS SCLK SDIO_1 I7 (I1) I5 (I3) I3 (I5) I1 (I7) D7 (D1) D5 (D3) D3 (D5) D1 (D7) SDIO_0 I6 (I0) I4 (I2) I2 (I4) I0 (I6) D6 (D0) D4 (D2) D2 (D4) D0 (D6) 05252-126 I7 (I0) Figure 44.
Data Sheet AD9958 DATA TRANSFER CYCLE INSTRUCTION CYCLE CS I6 (I1) I7 (I0) SDIO_0 I5 (I2) I4 (I3) I3 (I4) I2 (I5) I1 (I6) I0 (I7) D7 (D0) D6 (D1) D5 (D2) D4 (D3) D3 (D4) D2 (D5) D1 (D6) D0 (D7) 05252-128 SCLK Figure 46.
AD9958 Data Sheet REGISTER MAPS AND BIT DESCRIPTIONS REGISTER MAPS Table 28.
Data Sheet AD9958 Table 29. Channel Register Map Register Name (Serial Address) Channel Function Register 1 (CFR) (0x03) Bit Range [23:16] [15:8] [7:0] Channel Frequency Tuning Word 01 (CFTW0) (0x04) Channel Phase Offset Word 01 (CPOW0) (0x05) Amplitude Control Register (ACR) (0x06) Linear Sweep Ramp Rate1 (LSRR) (0x07) LSR Rising Delta Word1 (RDW) (0x08) LSR Falling Delta Word1 (FDW) (0x09) Bit 7 (MSB) Bit 6 Amplitude freq.
AD9958 Data Sheet Table 30.
Data Sheet AD9958 DESCRIPTIONS FOR CONTROL REGISTERS Channel Select Register (CSR)—Address 0x00 One byte is assigned to this register. The CSR determines if channels are enabled or disabled by the status of the two channel enable bits. Both channels are enabled by their default state. The CSR also determines which serial mode of operation is selected. In addition, the CSR offers a choice of MSB first or LSB first format. Table 31.
AD9958 Bit 6 Mnemonic External power-down mode 5 SYNC_CLK disable 4 DAC reference power-down 3:2 1 Open Manual hardware sync 0 Manual software sync Data Sheet Description 0 = the external power-down mode is in fast recovery power-down mode (default). In this mode, when the PWR_DWN_CTL input pin is high, the digital logic and the DAC digital logic are powered down. The DAC bias circuitry, PLL, oscillator, and clock input circuitry are not powered down.
Data Sheet AD9958 DESCRIPTIONS FOR CHANNEL REGISTERS Channel Function Register (CFR)—Address 0x03 Three bytes are assigned to this register. Table 34.
AD9958 Data Sheet Channel Frequency Tuning Word 0 (CFTW0)—Address 0x04 Four bytes are assigned to this register. Table 35. Description for CFTW0 Bit 31:0 Mnemonic Frequency Tuning Word 0 Description Frequency Tuning Word 0 for each channel. Channel Phase Offset Word 0 (CPOW0)—Address 0x05 Two bytes are assigned to this register. Table 36. Description for CPOW0 Bit 15:14 13:0 Mnemonic Open Phase Offset Word 0 Description Phase Offset Word 0 for each channel.
Data Sheet AD9958 Linear Sweep Ramp Rate (LSRR)—Address 0x07 Two bytes are assigned to this register. Table 38. Description for LSRR Bit 15:8 7:0 Mnemonic Falling sweep ramp rate (FSRR) Rising sweep ramp rate (RSRR) Description Linear falling sweep ramp rate. Linear rising sweep ramp rate. LSR Rising Delta Word (RDW)—Address 0x08 Four bytes are assigned to this register. Table 39. Description for RDW Bit 31:0 Mnemonic Rising delta word Description 32-bit rising delta-tuning word.
AD9958 Data Sheet OUTLINE DIMENSIONS 0.30 0.23 0.18 0.60 MAX 0.60 MAX 43 PIN 1 INDICATOR 7.85 7.75 SQ 7.65 1 0.50 BSC 6.25 6.10 SQ 5.95 EXPOSED PAD 29 TOP VIEW 1.00 0.85 0.80 SEATING PLANE 0.80 MAX 0.65 TYP 12° MAX 0.50 0.40 0.30 14 28 15 BOTTOM VIEW 0.25 MIN 6.50 REF 0.05 MAX 0.02 NOM COPLANARITY 0.20 REF 0.08 SIDE VIEW PIN 1 INDICATOR 56 42 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.
