User Manual

Hard Disk Drive Specification

Registers

In Serial ATA, the host adapter contains a set of registers that shadow the contents of the traditional device

registers, referred to as the Shadow Register Block. Shadow Register Block registers are interface registers used

for delivering commands to the device or posting status from the device. About details, please refer to the Serial

ATA Specification.

In the following cases, the host adapter sets the BSY bit in its shadow Status Register and transmits a FIS to the

device containing the new contents.

 Command register is written in the Shadow Register Block

 Device Control register is written in the Shadow Register Block with a change of state of the SRST bit

 COMRESET is requested

Alternate Status Register

BSY

RDY

DSC

/SERV

DRQ

COR

IDX

ERR

Table 25 Alternate Status Register

This register contains the same information as the Status Register. The only difference is that reading this register

does not imply interrupt acknowledge or clear a pending interrupt. See 8.11 “Status Register” on the page 51 for the

definition of the bits in this register.

Command register

This register contains the command code being sent to the device. Command execution begins immediately after

this register is written. The command set is shown in Table 93 Command Set on page 129.

All other registers required for the command must be set up before writing the Command Register.

Cylinder High Register

This register contains the high order bits of the starting cylinder address for any disk access. At the end of the

command, this register is updated to reflect the current cylinder number.

In LBA Mode this register contains Bits 16-23. At the end of the command, this register is updated to reflect the

current LBA Bits 16-23.

The cylinder number may be from zero to the number of cylinders minus one.

When 48-bit addressing commands are used, the “most recently written” content contains LBA Bits 16-23, and the

“previous content” contains Bits 40-47. The 48-bit Address feature set is described in 9.12.