Freescale Semiconductor Technical Data Document Number: MM908E621 Rev 4.0, 6/2007 Integrated Quad Half-Bridge and Triple High-Side with Embedded MCU and LIN for High End Mirror 908E621 QUAD HALF-BRIDGE AND TRIPLE HIGHSIDE SWITCH WITH EMBEDDED MCU AND LIN The 908E621 is an integrated single-package solution that includes a high-performance HC08 microcontroller with a SMARTMOSTM analog control IC.
Single External IRQ Module 24 Integral System Integration Module PTA6/SS PTA5/SPSCK PTA4/KBD4 PTA3/KBD3 PTA2/KBD2 PTA1/KBD1 PTA0/KBD0 PTB7/AD7/TBCH1 PTB6/AD6/TBCH0 PTB5/AD5 PTB4/AD4 PTB3/AD3 PTB2/AD2 PTB0/AD0 PTB0/AD0 Security Module Power-ON Reset Module VREFH VDDA 10 Bit Analog-toVREFL Digital Converter Module VSSA VDD POWER VSS IRQ RST OSC2 Internal Clock OSC1 Generator Module User Flash Vector Space, 36 Bytes DDRA PORT A PTB0/AD0 ADOUT SPSCK MOSI PTC1/MOSI PTA5/SPSCK MISO SS PWM PTC
TERMINAL CONNECTIONS TERMINAL CONNECTIONS Transparent Top View of Package PTC4/OSC1 PTC3/OSC2 PTC2/MCLK PTB5/AD5 PTB4/AD4 PTB3/AD3 1 54 2 53 3 52 4 51 5 50 6 49 IRQ RST 7 48 8 47 (PTD0/TACH0/BEMF -> PWM) PTD1/TACH1 9 46 10 45 RST_A IRQ_A 11 44 12 43 LIN A0CST A0 GND1 HB4 VSUP1 GND2 HB3 VSUP2 NC NC TESTMODE GND3 HB2 VSUP3 13 14 15 42 Exposed Pad 41 40 16 39 17 38 18 37 19 36 20 35 21 34 22 33 23 32 24 31 25 30 26 29 27 28 PTA0/KBD0 PTA1/KBD1 PTA2/KBD
TERMINAL CONNECTIONS Table 1. Terminal Definitions (continued) A functional description of each terminal can be found in the Functional Terminal Description section beginning on page 21. Die Terminal Terminal Name Formal Name Definition MCU 45 VSSA/VREFL VDDA/VREFH ADC Supply and 48 Reference Terminals These terminals are the power supply and voltage reference terminals for the analog-to-digital converter (ADC).
TERMINAL CONNECTIONS Table 1. Terminal Definitions (continued) A functional description of each terminal can be found in the Functional Terminal Description section beginning on page 21. Die Terminal Terminal Name Formal Name Definition Analog 42 VDD Voltage Regulator Output The +5.0 V voltage regulator output terminal is intended to supply the embedded microcontroller.
MAXIMUM RATINGS MAXIMUM RATINGS Table 2. Maximum Ratings All voltages are with respect to ground unless otherwise noted. Exceeding limits on any terminal may cause permanent damage to the device. Rating Symbol Value Unit Analog Chip Supply Voltage under Normal Operation (Steady-State) VSUP(SS) -0.3 to 28 Analog Chip Supply Voltage under Transient Conditions (1) VSUP(PK) -0.3 to 40 VDD -0.3 to 5.5 VIN(ANALOG) -0.3 to 5.5 VIN(MCU) VSS -0.3 to VDD +0.
MAXIMUM RATINGS Table 2. Maximum Ratings (continued) All voltages are with respect to ground unless otherwise noted. Exceeding limits on any terminal may cause permanent damage to the device. Rating Symbol Value Unit Operating Ambient Temperature (3) TA -40 to 85 °C Operating Junction Temperature (4) TJ -40 to 125 °C Storage Temperature TSTG -40 to 150 °C Peak Package Reflow Temperature During Reflow (6), (7) TPPRT Note 7 °C THERMAL RATINGS Notes 3.
STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics All characteristics are for the analog chip only. Refer to the 68HC908EY16 datasheet for characteristics of the microcontroller chip. Characteristics noted under conditions 9.0 V ≤ VSUP ≤ 16 V, -40°C ≤ TJ ≤ 125°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics (continued) All characteristics are for the analog chip only. Refer to the 68HC908EY16 datasheet for characteristics of the microcontroller chip. Characteristics noted under conditions 9.0 V ≤ VSUP ≤ 16 V, -40°C ≤ TJ ≤ 125°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit VLVRON 3.8 4.
STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics (continued) All characteristics are for the analog chip only. Refer to the 68HC908EY16 datasheet for characteristics of the microcontroller chip. Characteristics noted under conditions 9.0 V ≤ VSUP ≤ 16 V, -40°C ≤ TJ ≤ 125°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics (continued) All characteristics are for the analog chip only. Refer to the 68HC908EY16 datasheet for characteristics of the microcontroller chip. Characteristics noted under conditions 9.0 V ≤ VSUP ≤ 16 V, -40°C ≤ TJ ≤ 125°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics (continued) All characteristics are for the analog chip only. Refer to the 68HC908EY16 datasheet for characteristics of the microcontroller chip. Characteristics noted under conditions 9.0 V ≤ VSUP ≤ 16 V, -40°C ≤ TJ ≤ 125°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics (continued) All characteristics are for the analog chip only. Refer to the 68HC908EY16 datasheet for characteristics of the microcontroller chip. Characteristics noted under conditions 9.0 V ≤ VSUP ≤ 16 V, -40°C ≤ TJ ≤ 125°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics (continued) All characteristics are for the analog chip only. Refer to the 68HC908EY16 datasheet for characteristics of the microcontroller chip. Characteristics noted under conditions 9.0 V ≤ VSUP ≤ 16 V, -40°C ≤ TJ ≤ 125°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 4. Dynamic Electrical Characteristics All characteristics are for the analog chip only. Please refer to the 68HC908EY16 datasheet for characteristics of the microcontroller chip. Characteristics noted under conditions 9.0 V ≤ VSUP ≤ 16 V, -40°C ≤ TJ ≤ 125°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
DYNAMIC ELECTRICAL CHARACTERISTICS Table 4. Dynamic Electrical Characteristics (continued) All characteristics are for the analog chip only. Please refer to the 68HC908EY16 datasheet for characteristics of the microcontroller chip. Characteristics noted under conditions 9.0 V ≤ VSUP ≤ 16 V, -40°C ≤ TJ ≤ 125°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
MICROCONTROLLER PARAMETRICS MICROCONTROLLER PARAMETRICS Table 5. Microcontroller For a detailed microcontroller description, refer to the MC68HC908EY16 datasheet. Module Description Core High Performance HC08 Core with a Maximum Internal Bus Frequency of 8.
TIMING DIAGRAMS TIMING DIAGRAMS Transient Pulse Generator LIN, L0 10k 1nF Note: Waveform in accordance to ISO7637 part 1, test pulses 1, 2, 3a and 3b. Figure 4. Test Circuit for Transient Test Pulses VSUP VSUP R0 TXD LIN RXD C0 R0R0 and C0C0 Combinations: and combinations: • 1.0 kΩ and 1.0 nF - 1k Ohm and 1nF • 600 Ω Ohm and 6.8 - 660 andnF 6.8nF • 500 Ω Ohm and 10 - 500 andnF10nF Figure 5. Test Circuit for LIN Timing Measurements TXD tREC-MAX VLIN tDOM-MIN 58.1% VSUP LIN 74.
TIMING DIAGRAMS TXD tREC-MAX VLIN tDOM-MIN 61.6% VSUP LIN 77.8% VSUP 40% VSUP 60% VSUP 25.1% VSUP 38.9% VSUP tDOM-MAX tREC-MIN RXD tRL tRH Figure 7. LIN Timing Measurements for Slow Slew Rate VLIN_REC Vrec LIN 0.4VSUP 0.4 VSUP Dominant Level Dominant level IRQ_A tTpropWL PROPWL tTwake WAKE Figure 8. Wake-Up Stop Mode Timing Vrec VLIN_REC LIN 0.4VSUP 0.4 V SUP Dominant Level Dominant level VDD tTpropWL PROPWL tTwake WAKE Figure 9.
TIMING DIAGRAMS VSUP VDD RST_A TRST TNORMREQ Figure 10.
FUNCTIONAL DESCRIPTION INTRODUCTION FUNCTIONAL DESCRIPTION INTRODUCTION The 908E621 was designed and developed as a highly integrated and cost-effective solution for automotive and industrial applications. For automotive body electronics, the 908E621 is well suited to perform complete mirror control via a three-wire LIN bus. This device combines an HC908EY16 MCU core with flash memory together with a SmartMOS IC chip. The SmartMOS IC chip combines power and control in one chip.
FUNCTIONAL DESCRIPTION FUNCTIONAL TERMINAL DESCRIPTION EXTERNAL RESET TERMINAL (RST) HALL-EFFECT SENSOR INPUT TERMINAL (H0) A logic [0] on the RST terminal forces the MCU to a known startup state. RST is bidirectional, allowing a reset of the entire system. It is driven LOW when any internal reset source is asserted. The Hall-effect sensor input terminal H0 provides an input for Hall-effect sensors (2pin or 3pin) or a switch.
FUNCTIONAL DESCRIPTION FUNCTIONAL TERMINAL DESCRIPTION INTERRUPT TERMINAL (IRQ_A) TEST MODE TERMINAL (TESTMODE) IRQ_A is the interrupt output terminal of the analog die indicating errors or wake-up events. It is an open drain with pullup resistor and must be connected to the IRQ terminal of the MCU. This terminal is for test purpose only. In the application this terminal has to be forced to GND.
FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES 908E621 ANALOG DIE MODES OF OPERATION The different modes can be selected by the STOP and SLEEP bits in the System Control Register. Figure 11 describes how transitions are done between the different operating modes and Table 6, page 26, gives an overview of the operating modes.
FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES Stop mode has a higher current consumption than Sleep mode, but allows a quicker wake-up. Additionally the wakeup sources can be selected (maskable) which is not possible in Sleep mode. Figure 12 show the procedure to enter the Stop mode and how the system is waking up. MCU Power Die behaves like a power on reset. The wake-up / reset source can be evaluated by the L0WF and/or LINWF bits in the Reset Status Register.
FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES Table 6.
FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES input). The interrupt function is available if the input is selected as General Purpose or as 2pin Hallsensor input. The interrupt is maskable with the H0IE bit in the Interrupt Mask Register. During Stop and Sleep mode the H0I circuitry is disabled. LVIF - Low Voltage Flag Bit L0 input Interrupt The L0 interrupt flag L0IF is set in run mode by a state change of the L0F flag (rising or falling edge).
FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES INTERRUPT MASK REGISTER (IMR) 1 = high temperature reset is disabled 0 = high temperature reset is enabled Register Name and Address: IMR - $09 Bit7 6 5 4 3 2 1 Bit0 L0IE H0IE LINIE HTRD HTIE LVIE HVIE PSFIE Read Write Reset 0 0 0 0 0 0 0 0 Note: Disabling of the high temperature reset can lead to a destruction of the part in cases of high temperature.
FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES RESETS The 908E621 has four internal and one external reset source. Each internal reset event will cause a reset pin low for tRST (1.25 ms typical), after the reset event is gone. SPI REGISTERS WDRE WD Reset Sensor Reset SPI Register (not RSR) VDD HTRD HTR Reset Sensor Clear RSR and set POR Bit RST_A RSR POR internal VREG LVR Main VREG MONO FLOP Pulse Duration after reset event is removed Figure 15. Internal Reset Routing RESET SOURCE Register.
FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES In addition the register includes two flags which will indicate the source of a wake-up from Sleep mode: Either LIN bus activity or an event on the L0 wake-up input terminal. 1 = reset source is watchdog 0 = no watchdog reset HTR— High Temperature Reset bit Register Name and Address: RSR - $0D Bit7 6 5 4 3 POR PINR WDR HTR LVR 1 0 0 0 0 Read 2 1 Bit0 This read/write bit is set if the chip temperature exceeds a certain value.
FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES the LIN bus at recessive level. In case of a LIN bus short to GND, this feature will reduce the current consumption in STOP and SLEEP modes.
FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES A0 INPUT AND ANALOG MULTIPLEXER A0 is internally connected to the analog multiplexer. This terminal offers a switchable current source. To read the Analog Input the terminal has to be selected with the SS[3:0] bits in the A0MUCTL register. A0 - Analog Input Input A0 is an analog input used for reading switches or as analog inputs for potentiometers, NTC, etc.
FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES Table 7. A0 Current Source Level Selection Bits analog multiplexer is integrated in the analog die. This multiplexer has eleven different sources, which can be selected with the SS[3:0] bits in the A0MUCTL register. CSSEL1 CSSEL0 0 0 40µA 0 1 120µA Half-bridge (HB1:HB4) Current Recopy 1 0 320µA The multiplexer is connected to the four current sense circuits on the low side FET of the half bridges.
FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES VDD 10k H0PD VSUP H0MS H0MS H0 H0EN H0F H0EN Current Sense Figure 18. General purpose / hall-effect sensor input (H0) Current Coded Hallsensor Input After switching on the hallport (H0EN = “1”) the hallsensor needs some time to stabilize the output. In RUN mode the software has to take care about waiting for a few µs (40) before sensing the hallflags.
FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES Figure 19. H0 used as 2-pin hallsensor input General Purpose Input H0 is selected as general purpose input, if the H0MS bit in the H0/L0 Status and Control Register (HLSCTL) is cleared. In this mode the input is usable as standard 5V input. The H0 VDD input has a selectable internal pull-up resistors. The pull-up can be switched off with the H0PD bit in the H0/L0 Status and Control Register (HLSCTL). After reset the internal pull-up is enabled.
FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES Wake-up input L0 H0F — H0 Flag Bit The device provides one wake-up capable input for reading VSUP or VDD related signals. RUN mode The actual input state is reflected in bit L0F of the H0/L0 Status and Control register (HLSCTL). The L0 terminal offers an interrupt capability on rising and falling edge. The interrupt can be enabled with the L0IE bit in the Interrupt Mask register.
FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES VSUP On/Off High-Side Driver Status Charge Pump Overtemperature Protection Overcurrent Protection PWM Control HBx On/Off Status PWM Low-Side Driver Current Recopy Current Limitation Active Clamp Overcurrent Protection GND Figure 22.
FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES Half-Bridge Control Each output MOSFET can be controlled individually. The general enable of the circuitry is done by setting PSON in the System Control Register (SYSCTL). The HBx_L and HBx_H bits form one half bridge. It is not possible to switch on both MOSFETs in one half-bridge at the same time. If both bits are set, the high-side MOSFET is in PWM mode.
FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES 1 = recirculation via switched on low-side MOSFET 0 = recirculation via low-side free wheeling diode Half-Bridge Overvoltage/Undervoltage Protection The half-bridge outputs are protected against undervoltage and overvoltage conditions. This protection is done by the low and high voltage interrupt circuitry. If one of this flags (LVIF, HVIF) is set, the outputs are automatically disabled if the VIS bit in the System Control Register (SYSCTL) is cleared.
FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES Table 10. High-Side Configuration Bits HSxPWM HSxON 0 0 High-side MOSFET off 0 1 High-side MOSFET on, in case of overcurrent the overcurrent flag (HSxOCF) is set and the High-side MOSFET is turned off 1 0 Mode In this mode the PWM duty cycle is either controlled by the PWM input signal or in case the overcurrent shutdown value is reached by the part itself.
FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES HS Current HS Over-Current Shutdown Threshold t PWM Terminal t Figure 24. Inrush Current Limitation on HS Outputs High-Side Current Recopy High-Side Out Register (HSOUT) Each High-Side has an additional sense output to allow a current recopy feature. This sense source is internally connected to a shunt resistor. The drop voltage is amplified and switched to the Analog Multiplexer.
FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES HSxPWM — High-Side PWM on/off Bits These read/write bits enable the PWM control of the HighSide Fet’s. Reset clears the HSxPWM bits. 1 = High-Side x is controlled by PWM input signal 0 = High-Side x is not controlled by PWM input signal Register Name and Address: HSSTAT - $04 Read Write HVDD OCF Reset 6 5 4 3 0 0 0 0 0 0 0 0 2 1 Bit0 HS3O CF HS2O CF HS1O CF 0 0 0 In order to safely Stop mode all other bits (Bit7-Bit2) have to be “0”.
FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES SRS0-1 — LIN Slew rate Select Bits H0F — H0 Failure Bit These read/write bits enable the user to select the appropriate LIN slew rate for different Baudrate configurations. Reset clears the SRS1:0 bits. This read only bit is a copy of the H0OCF bit in the H0/L0 Status and Control Register (HLSCTL) 1 = overcurrent detected on H0 0 = no overcurrent on H0 Table 11.
FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES function is enabled it is not possible to disable it via software. Reset clears the WDRE bit. To prevent a Watchdog reset, the Watchdog timer has to be cleared in the Window Open frame. This is done by writing a logic “1” to the WDRST bit in the Watchdog Control register (WDCTL). The actual reset of the watchdog counter occurs at the end of the corresponding SPI transmission with the rising edge of the SS signal.
FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES STOP mode SLEEP mode During STOP mode, the Stop mode regulator will take care of suppling a regulated output voltage. The Stop mode regulator has a limited output current capability. In Sleep mode the main voltage regulator external VDD is turned off and the LVR circuitry will force the RST_A terminal low.
FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS LOGIC COMMANDS AND REGISTERS 908E621 SERIAL PHERIPHERAL INTERFACE (SPI) The Serial Peripheral Interface (SPI) creates the communication link between the MCU and the analog die. A complete data transfer via the SPI, consists of 2 bytes. The master sends address and data, the slave returns system status and the data of the selected address.
FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS Master Data Byte This byte includes data to be written or no valid data during a read operation. Slave Data Byte This byte includes the contents of selected register, during write operation in includes the register content prior to write operation. Slave Status Byte This byte includes always the contents of the system status register ($0C) independent if it is a write or read operation or which register was selected.
FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS SPI REGISTER OVERVIEW TABLE 13 SUMMARIZES THE SPI REGISTER ADDRESSES AND THE BIT NAMES OF EACH REGISTER. Table 13.
FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS FACTORY TRIMMING AND CALIBRATION To enhance the ease-of-use of the 908E621, various parameters (e.g. ICG trim value) are stored in the flash memory of the device. The following flash memory locations are reserved for this purpose and might have a value different from the “empty” ($FF) state: Watchdog Period Range Value (AWD Trim) The window watchdog supervises device recover from e.g. code runaways.
FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS Analog Die System Trim Values For improved application performance and to ensure the outlined datasheet values the analog die needs to be trimmed. For this purpose 3 trim values are stored in the Flash memory at address $FDC4 - $FDC6.
FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS CRHBHC1 CRHBHC0 Adjustment 1 0 5% 1 1 10% System Trim Register 3 (SYSTRIM3) Register Name and Address: IFBHSTRIM - $11 CRHB5:3 - Current Recopy HB3:4 Trim Bits These write only bits are for trimming of the current recopy of the half-bridge HB3 and HB4 (CSA=1). The provided trim values have to be copied into these bits after every reset. Reset clears the CRHB5:3 bits.
FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS CRHS2:0 - Current Recopy HS1 Trim Bits These write only bits are for trimming of the current recopy of the high-side HS1. The provided Trim values have to be copied into these bits after every reset. Reset clears the CRHS2:0 bits.
TYPICAL APPLICATIONS TYPICAL APPLICATIONS DEVELOPMENT SUPPORT As the 908E621 has the MC68HC908EY16 MCU embedded, typically all the development tools available for the MCU also apply for this device.
TYPICAL APPLICATIONS PCB level programming system has to be powered up providing VSUP (see Figure 31).. If the IC is soldered onto the pcb board, its typically not possible to separately power the MCU with +5V. The whole VDD VSUP + 100nF 47µF VSUP[1:8] VDD GND[1:4] VSS VDDA/VREFH RST EVDD RST_A VDD 1 1µF 16 + + 3 4 1µF VCC C1+ C1- GND C2+ V+ + V5 RS232 DB-9 100nF IRQ VTST 4.7µF VSSA/VREFL MM908E621 IRQ_A EVSS 1µF 15 VDD 1µF + 2 10k 9.
TYPICAL APPLICATIONS EMC/EMI RECOMMENDATIONS MCU digital supply terminals (EVDD and EVSS) This paragraph gives some device specific recommendations to improve EMC/EMI performance. Further generic design recommendations can be e.g. found on the Freescale web site www.freescale.com. VSUP terminals (VSUP[1:8]) Fast signal transitions on MCU terminals place high, shortduration current demands on the power supply. To prevent noise problems, take special care to provide power supply bypassing at the MCU.
TYPICAL APPLICATIONS 1 54 2 53 3 52 4 51 5 50 49 VDDA/VREFH 48 8 EVDD 47 9 EVSS 46 10 VSSA/VREFL 45 11 44 12 43 VDD 42 908E621 15 16 40 GND1 39 17 38 18 VSUP1 19 GND2 VSUP8 VSUP2 GND 33 23 VSUP6 32 VSUP5 31 GND3 GND4 30 VSUP3 VSUP4 24 26 29 D1 28 VBAT V1 27 35 34 22 25 37 36 VSUP7 20 21 41 C1 14 LIN VSS C2 C5 13 C4 7 C3 6 LIN L1 Figure 33. PCB Layout Recommendations . Table 23.
PACKAGE DIMENSIONS PACKAGE DIMENSIONS Important For the most current revision of the package, visit www.freescale.com and do a keyword search on the 98A drawing number: 98ARL10519D.
ADDITIONAL INFORMATION THERMAL ADDENDUM (REV 1.0) ADDITIONAL INFORMATION 908E621 THERMAL ADDENDUM (REV 1.0) INTEGRATED QUAD H-BRIDGE AND TRIPLE HIGH-SIDE DRIVER WITH EMBEDDED MCU AND LIN FOR MIRROR Introduction This thermal addendum ia provided as a supplement to the MM908E621 technical data sheet. The addendum provides thermal performance information that may be critical in the design and development of system applications.
ADDITIONAL INFORMATION THERMAL ADDENDUM (REV 1.
ADDITIONAL INFORMATION THERMAL ADDENDUM (REV 1.0) Thermal Resistance [ºC/W] 60 50 40 30 20 x 10 RθJA11 RθJA22 RθJA12 = RθJA21 0 0 300 600 Heat spreading area A [mm²] Figure 36. Device on Thermal Test Board RθJA Thermal Resistance [ºC/W] 100 10 1 x 0.1 1.00E-03 1.00E-02 RθJA11 RθJA22 RθJA12 = RθJA21 1.00E-01 1.00E+00 1.00E+01 1.00E+02 1.00E+03 1.00E+04 Time[s] Figure 37. Transient Thermal Resistance RθJA (1.
REVISION HISTORY REVISION HISTORY REVISION DATE DESCRIPTION OF CHANGES 3.0 2/2007 • Implemented Revision History page • Changed Table 3, Ststic Electrical Characteristics, Hall-Effect Sensor Input H0 - 2pin Hall Sensor Input Mode (H0MS = 1), Sense Current Hysteresis on page 14 from a Minimum of 800 to 600 and Typical from 1100 to none. • Removed “Advance” watermark and updated to final Data Sheet.
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