Data Sheet

ManualsBrandsUnbranded ManualsActive ComponentsLogic IC - Flip-Flop CD74HCT273E Master reset Non-inverting DIP 20

Data sheet acquired from Harris Semiconductor

SCHS174B

Features

• Common Clock and Asynchronous Master Reset

• Positive Edge Triggering

• Buffered Inputs

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

C to 125

• Balanced Propagation Delay and Transition Times

• Signiﬁcant Power Reduction Compared to LSTTL

Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

= 30%, N

= 30% of V

at V

= 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

= 0.8V (Max), V

= 2V (Min)

- CMOS Input Compatibility, I

≤ 1µA at V

, V

Description

The ’HC273 and ’HCT273 high speed octal D-Type flip-flops

with a direct clear input are manufactured with silicon-gate

CMOS technology. They possess the low power consumption

of standard CMOS integrated circuits.

Information at the D inputis transferred to the Q outputs on

the positive-going edge of the clock pulse. All eight ﬂip-ﬂops

are controlled by a common clock (CP) and a common reset

(

MR). Resetting is accomplished by a low voltage level

independent of the clock. All eight Q outputs are reset to a

logic 0.

Pinout

CD54HC273, CD54HCT273

(CERDIP)

CD74HC273, CD74HCT273

(PDIP, SOIC)

TOP VIEW

Ordering Information

PART NUMBER TEMP. RANGE (

C) PACKAGE

CD54HC273F3A -55 to 125 20 Ld CERDIP

CD74HC273E -55 to 125 20 Ld PDIP

CD74HC273M -55 to 125 20 Ld SOIC

CD74HC273M96 -55 to 125 20 Ld SOIC

CD54HCT273F3A -55 to 125 20 Ld CERDIP

CD74HCT273E -55 to 125 20 Ld PDIP

CD74HCT273M -55 to 125 20 Ld SOIC

CD74HCT273M96 -55 to 125 20 Ld SOIC

NOTE: When ordering, use the entire part number. The sufﬁx 96

denotes tape and reel.

GND

February 1998 - Revised May 2003

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

CD54HC273, CD74HC273,

CD54HCT273, CD74HCT273

High-Speed CMOS Logic

Octal D-Type Flip-Flop with Reset

[ /Title

(CD74

HC273

CD74

HCT27

Sub-

ect

(High

Speed

CMOS

Logic

Octal

D-

Type

Flip-

Summary of content (17 pages)

PAGE 1
[ /Title (CD74 HC273 , CD74 HCT27 3) /Subject (High Speed CMOS Logic Octal DType Flip- CD54HC273, CD74HC273, CD54HCT273, CD74HCT273 Data sheet acquired from Harris Semiconductor SCHS174B High-Speed CMOS Logic Octal D-Type Flip-Flop with Reset February 1998 - Revised May 2003 Features Description • Common Clock and Asynchronous Master Reset The ’HC273 and ’HCT273 high speed octal D-Type flip-flops with a direct clear input are manufactured with silicon-gate CMOS technology.
PAGE 2
CD54/74HC273, CD54/74HCT273 Functional Diagram CLOCK CP DATA INPUTS D0 Q0 D1 Q1 D2 Q2 D3 Q3 D4 Q4 D5 Q5 D6 Q6 D7 Q7 DATA OUTPUTS RESET MR TRUTH TABLE INPUTS OUTPUT RESET (MR) CLOCK CP DATA Dn Q L X X L H ↑ H H H ↑ L L H L X Q0 H = High Voltage Level, L = Low Voltage Level, X = Don’t Care, ↑ = Transition from Low to High Level, Q0 = Level Before the Indicated Steady-State Input Conditions Were Established.
PAGE 3
CD54/74HC273, CD54/74HCT273 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Drain Current, per Output, IO For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .
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CD54/74HC273, CD54/74HCT273 DC Electrical Specifications (Continued) TEST CONDITIONS SYMBOL VI (V) High Level Input Voltage VIH - - Low Level Input Voltage VIL - High Level Output Voltage CMOS Loads VOH VIH or VIL PARAMETER 25oC IO (mA) VCC (V) -40oC TO 85oC -55oC TO 125oC MIN TYP MAX MIN MAX MIN MAX UNITS 4.5 to 5.5 2 - - 2 - 2 - V - 4.5 to 5.5 - - 0.8 - 0.8 - 0.8 V -0.02 4.5 4.4 - - 4.4 - 4.4 - V -4 4.5 3.98 - - 3.84 - 3.7 - V 0.02 4.
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CD54/74HC273, CD54/74HCT273 Prerequisite For Switching Specifications PARAMETER 25oC -40oC TO 85oC -55oC TO 125oC SYMBOL TEST CONDITIONS VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS tW - 2 80 - - 100 - 120 - ns 4.5 16 - - 20 - 24 - ns 6 14 - - 17 - 20 - ns 2 60 - - 75 - 70 - ns 4.5 12 - - 15 - 18 - ns 6 10 - - 13 - 15 - ns 2 3 - - 3 - 3 - ns 4.5 3 - - 3 - 3 - ns 6 3 - - 3 - 3 - ns 2 50 - - 65 - 75 - ns 4.
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CD54/74HC273, CD54/74HCT273 Switching Specifications PARAMETER Input tr, tf = 6ns (Continued) 25oC -40oC TO 85oC -55oC TO 125oC SYMBOL TEST CONDITIONS VCC (V) TYP MAX MAX MAX UNITS CPD - 5 25 - - - pF CL = 50pF 4.5 - 30 38 45 ns CL = 15pF 5 12 - - - ns Power Dissipation Capacitance (Notes 3, 4) HCT TYPES Propagation Delay, Clock to Output (Figure 4) tPLH, tPHL Propagation Delay, MR to Output (Figure 4) tPHL CL = 50pF 4.
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CD54/74HC273, CD54/74HCT273 Test Circuits and Waveforms trCL tfCL trCL CLOCK INPUT (Continued) VCC 90% GND tH(H) GND tH(H) VCC DATA INPUT 50% tH(L) 3V 1.3V 1.3V 1.3V GND tSU(H) tSU(H) tSU(L) tTLH 90% OUTPUT tTHL 90% 50% 10% tTLH 90% 1.3V OUTPUT tREM 3V SET, RESET OR PRESET GND tTHL 1.3V 10% FIGURE 5. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME, AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED SEQUENTIAL LOGIC CIRCUITS tPHL 1.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 25-Sep-2013 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
PAGE 11
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant CD74HC273M96 SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1 CD74HCT273M96 SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CD74HC273M96 SOIC DW 20 2000 367.0 367.0 45.0 CD74HCT273M96 SOIC DW 20 2000 367.0 367.0 45.
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