Data Sheet

ManualsBrandsUnbranded ManualsActive ComponentsLogic IC - Flip-Flop CD74HC574E Standard Three-state, Non-inverting DIP 20

Data sheet acquired from Harris Semiconductor

SCHS183C

Features

• Buffered Inputs

• Common Three-State Output Enable Control

• Three-State Outputs

• Bus Line Driving Capability

• Typical Propagation Delay (Clock to Q) = 15ns at

= 5V, C

= 15pF, T

= 25

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

C to 125

• Balanced Propagation Delay and Transition Times

• Signiﬁcant Power Reduction Compared to LSTTL

Logic ICs

• HC Types

- 2-V to 6-V Operation

- High Noise Immunity: N

= 30%, N

= 30% of V

at V

= 5V

• HCT Types

- 4.5-V to 5.5-V Operation

- Direct LSTTL Input Logic Compatibility,

= 0.8V (Max), V

= 2V (Min)

- CMOS Input Compatibility, I

≤ 1µA at V

, V

Description

The ’HC374, ’HCT374, ’HC574, and ’HCT574 are octal D-type

flip-flops with 3-state outputs and the capability to drive 15

LSTTL loads. The eight edge-triggered flip-flops enter data into

their registers on the LOW to HIGH transition of clock (CP). The

output enable (

OE) controls the 3-state outputs and is

independent of the register operation. When

OE is HIGH, the

outputs are in the high-impedance state. The 374 and 574 are

identical in function and differ only in their pinout arrangements.

Ordering Information

PART NUMBER

TEMP. RANGE

(

C) PACKAGE

CD54HC374F3A -55 to 125 20 Ld CERDIP

CD54HC574F3A -55 to 125 20 Ld CERDIP

CD54HCT374F3A -55 to 125 20 Ld CERDIP

CD54HCT574F3A -55 to 125 20 Ld CERDIP

CD74HC374E -55 to 125 20 Ld PDIP

CD74HC374M -55 to 125 20 Ld SOIC

CD74HC374M96 -55 to 125 20 Ld SOIC

CD74HC574E -55 to 125 20 Ld PDIP

CD74HC574M -55 to 125 20 Ld SOIC

CD74HC574M96 -55 to 125 20 Ld SOIC

CD74HCT374E -55 to 125 20 Ld PDIP

CD74HCT374M -55 to 125 20 Ld SOIC

CD74HCT374M96 -55 to 125 20 Ld SOIC

CD74HCT574E -55 to 125 20 Ld PDIP

CD74HCT574M -55 to 125 20 Ld SOIC

CD74HCT574M96 -55 to 125 20 Ld SOIC

CD74HCT574PWR -55 to 125 20 Ld TSSOP

NOTE: When ordering, use the entire part number. The sufﬁxes

96 and R denote tape and reel.

February 1998 - Revised May 2004

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

CD54/74HC374, CD54/74HCT374,

CD54/74HC574, CD54/74HCT574

High-Speed CMOS Logic Octal D-Type Flip-Flop,

3-State Positive-Edge Triggered

[ /Title

(CD74

HC374

D74

HCT37

CD74

HC574

D74

HCT57

Summary of content (21 pages)

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[ /Title (CD74 HC374 , CD74 HCT37 4, CD74 HC574 , CD74 HCT57 CD54/74HC374, CD54/74HCT374, CD54/74HC574, CD54/74HCT574 Data sheet acquired from Harris Semiconductor SCHS183C February 1998 - Revised May 2004 High-Speed CMOS Logic Octal D-Type Flip-Flop, 3-State Positive-Edge Triggered Features Description • Buffered Inputs The ’HC374, ’HCT374, ’HC574, and ’HCT574 are octal D-type flip-flops with 3-state outputs and the capability to drive 15 LSTTL loads.
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CD54/74HC374, CD54/74HCT374, CD54/74HC574, CD54/74HCT574 Pinouts CD54HC574, CD54HCT574 (CERDIP) CD74HC574 (PDIP, SOIC) CD74HCT574 (PDIP, SOIC, TSSOP) TOP VIEW CD54HC374, CD54HCT374 (CERDIP) CD74HC374, CD74HCT374 (PDIP, SOIC) TOP VIEW OE 1 20 VCC OE 1 20 VCC Q0 2 19 Q7 D0 2 19 Q0 D0 3 18 D7 D1 3 18 Q1 D1 4 17 D6 D2 4 17 Q2 Q1 5 16 Q6 D3 5 16 Q3 Q2 6 15 Q5 D4 6 15 Q4 D2 7 14 D5 D5 7 14 Q5 D3 8 13 D4 D6 8 13 Q6 Q3 9 12 Q4 D7 9 12 Q7 GND 10 11 CP GND 10
PAGE 3
CD54/74HC374, CD54/74HCT374, CD54/74HC574, CD54/74HCT574 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Drain Current, per Output, IO For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . .
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CD54/74HC374, CD54/74HCT374, CD54/74HC574, CD54/74HCT574 DC Electrical Specifications (Continued) TEST CONDITIONS PARAMETER Quiescent Device Current 25oC -40oC TO 85oC -55oC TO 125oC SYMBOL VI (V) IO (mA) VCC (V) ICC VCC or GND 0 6 - - 8 - 80 - 160 µA - 6 - - ±0.5 - ±5.0 - ±10 µA Three- State Leakage VIL or VIH VO = VCC or GND Current MIN TYP MAX MIN MAX MIN MAX UNITS HCT TYPES High Level Input Voltage VIH - - 4.5 to 5.
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CD54/74HC374, CD54/74HCT374, CD54/74HC574, CD54/74HCT574 Prerequisite for Switching Specifications 25oC PARAMETER -40oC TO 85oC -55oC TO 125oC SYMBOL VCC (V) MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS fMAX 2 6 - - 5 - - 4 - - MHz 4.5 30 - - 25 - - 20 - - MHz 6 35 - - 29 - - 23 - - MHz 2 80 - - 100 - - 120 - - ns 4.5 16 - - 20 - - 24 - - ns 6 14 - - 17 - - 20 - - ns 2 60 - - 75 - - 90 - - ns 4.
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CD54/74HC374, CD54/74HCT374, CD54/74HC574, CD54/74HCT574 Switching Specifications CL = 50pF, Input tr, tf = 6ns (Continued) -40oC TO 85oC 25oC -55oC TO 125oC PARAMETER SYMBOL TEST CONDITIONS VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS Output Enable to Q tPZL, tPZH CL = 50pF 2 - - 150 - 190 - 225 ns 4.
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CD54/74HC374, CD54/74HCT374, CD54/74HC574, CD54/74HCT574 Test Circuits and Waveforms tWL + tWH = tfCL trCL 50% 10% 10% tf = 6ns tr = 6ns tTLH 90% INVERTING OUTPUT tPHL FIGURE 3. HC TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC tPLH FIGURE 4. HCT TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC trCL tfCL VCC tfCL GND 1.3V 0.3V GND tH(H) tH(L) VCC DATA INPUT 3V 2.7V CLOCK INPUT 50% tH(H) tTLH 1.3V 10% tPLH 10% GND tTHL 90% 50% 10% 90% 3V 2.
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CD54/74HC374, CD54/74HCT374, CD54/74HC574, CD54/74HCT574 Test Circuits and Waveforms 6ns (Continued) 6ns OUTPUT DISABLE 90% 50% 10% OUTPUTS ENABLED 2.7 1.3 OUTPUT HIGH TO OFF 50% OUTPUTS DISABLED FIGURE 7. HC THREE-STATE PROPAGATION DELAY WAVEFORM OTHER INPUTS TIED HIGH OR LOW OUTPUT DISABLE IC WITH THREESTATE OUTPUT GND 1.3V tPZH 90% OUTPUTS ENABLED OUTPUTS ENABLED 0.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 25-Sep-2013 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant CD74HC374M96 SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1 CD74HC574M96 SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1 CD74HCT374M96 SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CD74HC374M96 SOIC DW 20 2000 367.0 367.0 45.0 CD74HC574M96 SOIC DW 20 2000 367.0 367.0 45.0 CD74HCT374M96 SOIC DW 20 2000 367.0 367.0 45.0 CD74HCT574M96 SOIC DW 20 2000 367.0 367.0 45.0 CD74HCT574PWR TSSOP PW 20 2000 367.0 367.0 38.
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