Data Sheet

1
Data sheet acquired from Harris Semiconductor
SCHS121D
Features
• Buffered Inputs
• Typical Propagation Delay: 10ns at V
CC
= 5V,
C
L
= 15pF, T
A
= 25
o
C
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55
o
C to 125
o
C
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: N
IL
= 30%, N
IH
= 30% of V
CC
at V
CC
= 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V
IL
= 0.8V (Max), V
IH
= 2V (Min)
- CMOS Input Compatibility, I
l
≤ 1µA at V
OL
, V
OH
Pinout
CD54HC30, CD54HCT30 (CERDIP)
CD74HC30 (PDIP, SOIC, SOP, TSSOP)
CD74HCT30 (PDIP, SOIC)
TOP VIEW
Description
The ’HC30 and ’HCT30 each contain an 8-input NAND gate
in one package. They provide the system designer with the
direct implementation of the positive logic 8-input NAND
function. Logic gates utilize silicon gate CMOS technology to
achieve operating speeds similar to LSTTL gates with the
low power consumption of standard CMOS integrated cir-
cuits. All devices have the ability to drive 10 LSTTL loads.
The HCT logic family is functionally pin compatible with the
standard LS logic family.
A
B
C
D
E
F
GND
V
CC
NC
H
G
NC
NC
Y
1
2
3
4
5
6
7
14
13
12
11
10
9
8
Ordering Information
PART NUMBER
TEMP. RANGE
(
o
C) PACKAGE
CD54HC30F3A -55 to 125 14 Ld CERDIP
CD54HCT30F3A -55 to 125 14 Ld CERDIP
CD74HC30E -55 to 125 14 Ld PDIP
CD74HC30M -55 to 125 14 Ld SOIC
CD74HC30MT -55 to 125 14 Ld SOIC
CD74HC30M96 -55 to 125 14 Ld SOIC
CD74HC30NSR -55 to 125 14 Ld SOP
CD74HC30PW -55 to 125 14 Ld TSSOP
CD74HC30PWR -55 to 125 14 Ld TSSOP
CD74HC30PWT -55 to 125 14 Ld TSSOP
CD74HCT30E -55 to 125 14 Ld PDIP
CD74HCT30M -55 to 125 14 Ld SOIC
CD74HCT30MT -55 to 125 14 Ld SOIC
CD74HCT30M96 -55 to 125 14 Ld SOIC
NOTE: When ordering, use the entire part number. The suffixes 96
and R denote tape and reel. The suffix T denotes a small-quantity
reel of 250.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
© 2003, Texas Instruments Incorporated.
CD54/74HC30,
CD54/74HCT30
High Speed CMOS Logic
8-Input NAND Gate
[
/Title
(
CD54H
C
30,
C
D74H
C
30,
C
D74H
C
T30)
/
Subject
(
High
S
peed
C
MOS
L
ogic 8-
August 1997 - Revised September 2003