User's Manual

300-Watt Digital UHF Transmitter Chapter 4, Circuit Descriptions
DT830A, Rev. 1 4-8
VDC line. When the detected input signal
level at U9A, pin 2, falls below this
reference threshold, approximately 10 dB
below the normal input level, the output
of U9A, pin 1, goes to the +12 VDC rail.
This high is connected to the base of Q2,
which is forward biased, and creates a
current path from the -12 VDC line,
through the red Input Level Fault
Indicator LED DS1 (which lights), resistor
R54, and transistor Q2 to +12 VDC. The
high from U9A also connects through
diode CR16 to U9B, pin 5, whose output
at pin 7 goes high. The high connects
through range adjust pot R74 to J20,
which connects to the front panel-
mounted power adjust pot. This high
connects to U10A, pin 2, which causes it
to go low at output U10A, pin 1. The low
is applied through jumper W3 on J6 to
the pin-diode attenuator circuit that cuts
back the IF level and also cuts back the
output power level to 0. When the input
signal level increases above the threshold
level, the output power will rise as the
input level increases until normal output
power is reached.
The video input level at TP3 is also fed to
a sync-separator circuit, consisting of IC
U8, CR17, Q3, and associated
components, and then to a comparator
circuit made up of U9C and U9D. The
reference voltage for the comparators
are determined by the voltage divider,
consisting of R129, R64, R65, R66, and
R130, off of the -12 VDC line. When the
input signal level to the detector at TP3
falls below this reference threshold,
which acts as a loss of sync detector
circuit, the output of U9C and U9D goes
towards the -12 VDC rail, which is split,
with one part biasing on the transistor
Q5. A current path is then established
from the +12 VDC line through Q5,
resistors R69 and R137, and the red
Video Loss Indicator LED DS3, which
lights. When Q5 is on, it applies a high to
the gates of Q6 and Q7, causing them to
conduct; this applies video loss fault pull-
down outputs to J18, pins 5 and 2.
The other low output of U9C and U9D is
connected through CR20 to jack J5.
Jumper W2 on J5, in the cutback enable
position between pins 2 and 3, connects
the low to the base of Q4, which is
forward biased. If jumper W2 is in the
Disable position, between pins 1 and 2,
the automatic cutback will not operate.
With Q4 biased on, a level determined by
the setting of cutback level pot R71,
which is set at the factory to cut back the
output to approximately 25%, is applied
to U9B, pin 5. The output of U9B, pin 7,
goes low and is applied through the
power adjust pot to U10A, pin 2, whose
output goes low. This low is applied to
the pin-diode attenuator, which will cut
back the level of the output to
approximately 25%.
4.1.7.5 Pin-Diode Attenuator Circuit
The input IF signal is fed to the pin-diode
attenuator circuit, consisting of CR1 to
CR3. Each of the pin diodes contain a
wide, intrinsic region, which makes the
diodes function as voltage-variable
resistors at this intermediate frequency.
The value of the resistance is controlled
by the DC bias supplied to the diode. The
pin diodes are configured in a pi-type
attenuator configuration where CR1 is
the first shunt element, CR3 is the series
element, and CR2 is the second shunt
element. The control voltage, which can
be measured at TP1, originates either
from the ALC circuit, when jumper W3 on
J6 is in the ALC Auto position between
pins 1 and 2, or from pot R87 when the
jumper is in the Manual Gain position.
In the pin-diode attenuator circuit, a
current path exists from J6 through R6
and then through the diodes of the pin
attenuator. Changing the amount of
current through the diodes by forward
biasing them changes the IF output level
of the board. There are two extremes of
attenuation ranges for the pin-diode
attenuators. In the minimum attenuation
case, the voltage is measured as TP1
approaches the +12 VDC line. There is a
current path created through R6, through