Micro Controller User's Manual
Table Of Contents
- TMP92CZ26AXBG
- 1. Outline and Features
- 2. Pin Assignment and Pin Functions
- 3. Operation
- 3.1 CPU
- 3.2 Memory Map
- 3.3 Clock Function and Standby Function
- 3.4 Boot ROM
- 3.5 Interrupts
- 3.6 DMAC (DMA Controller)
- 3.7 Function of ports
- 3.7.1 Port 1 (P10 to P17)
- 3.7.2 Port 4 (P40 to P47)
- 3.7.3 Port 5 (P50 to P57)
- 3.7.4 Port 6 (P60 to P67)
- 3.7.5 Port 7 (P70 to P76)
- 3.7.6 Port 8 (P80 to P87)
- 3.7.7 Port 9 (P90 to P92, P96, P97)
- 3.7.8 Port A (PA0 to PA7)
- 3.7.9 Port C (PC0 to PC7)
- 3.7.10 Port F (PF0 to PF5, PF7)
- 3.7.11 Port G (PG0 to PG5)
- 3.7.12 Port J (PJ0 to PJ7)
- 3.7.13 Port K (PK0 to PK7)
- 3.7.14 Port L (PL0 to PL7)
- 3.7.15 Port M (PM1, PM2, PM7)
- 3.7.16 Port N (PN0 to PN7)
- 3.7.17 Port P (PP1 to PP7)
- 3.7.18 Port R (R0 to R3)
- 3.7.19 Port T (PT0 to PT7)
- 3.7.20 Port U (PU0 to PU7)
- 3.7.21 Port V (PV0 to PV4, PV6, PV7)
- 3.7.22 Port W (PW0 to PW7)
- 3.7.23 Port X (PX4, PX5 and PX7)
- 3.7.24 Port Z (PZ0 to PZ7)
- 3.8 Memory Controller (MEMC)
- 3.9 External Memory Extension Function (MMU)
- 3.10 SDRAM Controller (SDRAMC)
- 3.11 NAND Flash Controller (NDFC)
- 3.11.1 Features
- 3.11.1 Block Diagram
- 3.11.2 Operation Description
- 3.11.3 ECC Control
- 3.11.4 Description of Registers
- 3.11.5 An Example of Accessing NAND Flash of SLC Type
- 3.11.6 An Example of Accessing NAND Flash of MLC Type (When the valid data is processed as 518byte)
- 3.11.7 An Example of Connections with NAND Flash
- 3.12 8 Bit Timer (TMRA)
- 3.13 16 bit timer / Event counter (TMRB)
- 3.14 Serial Channels (SIO)
- 3.15 Serial Bus Interface (SBI)
- 3.16 USB Controller
- 3.16.1 Outline
- 3.16.2 900/H1 CPU I/F
- 3.16.3 UDC CORE
- 3.16.3.1 SFRs
- 3.16.3.2 EPx_FIFO Register (x: 0 to 3)
- 3.16.3.3 bmRequestType Register
- 3.16.3.4 bRequest Register
- 3.16.3.5 wValue Register
- 3.16.3.6 wIndex Register
- 3.16.3.7 wLength Register
- 3.16.3.8 Setup Received Register
- 3.16.3.9 Current_Config Register
- 3.16.3.10 Standard Request Register
- 3.16.3.11 Request Register
- 3.16.3.12 DATASET Register
- 3.16.3.13 EPx_STATUS Register (x: 0 to 7)
- 3.16.3.14 EPx_SIZE Register (x: 0 to 7)
- 3.16.3.15 FRAME Register
- 3.16.3.16 ADDRESS Register
- 3.16.3.17 EOP Register
- 3.16.3.18 Port Status Register
- 3.16.3.19 Standard Request Mode Register
- 3.16.3.20 Request Mode Register
- 3.16.3.21 COMMAND Register
- 3.16.3.22 INT_Control Register
- 3.16.3.23 USB STATE Register
- 3.16.3.24 EPx_MODE Register (x: 1 to 3)
- 3.16.3.25 EPx_SINGLE Register
- 3.16.3.26 EPx_BCS Register
- 3.16.3.27 USBREADY Register
- 3.16.3.28 Set Descriptor STALL Register
- 3.16.3.29 Descriptor RAM Register
- 3.16.4 Descriptor RAM
- 3.16.5 Device Request
- 3.16.6 Transfer mode and Protocol Transaction
- 3.16.7 Bus Interface and Access to FIFO
- 3.16.8 USB Device answer
- 3.16.9 Power Management
- 3.16.10 Supplement
- 3.16.11 Points to Note and Restrictions
- 3.17 SPIC (SPI Controller)
- 3.18 I2S (Inter-IC Sound)
- 3.19 LCD Controller (LCDC)
- 3.20 Touch Screen Interface (TSI)
- 3.21 Real time clock (RTC)
- 3.22 Melody / Alarm generator (MLD)
- 3.23 Analog-Digital Converter (ADC)
- 3.23.1 Control register
- 3.23.2 Operation
- 3.23.2.1 Analog Reference Voltages
- 3.23.2.2 Analog Input Channel(s) selection
- 3.23.2.3 Starting an AD Conversion
- 3.23.2.4 AD Conversion Modes and AD Conversion-End Interrupts
- 3.23.2.5 High-Priority Conversion Mode
- 3.23.2.6 AD Monitor Function
- 3.23.2.7 AD Conversion Time
- 3.23.2.8 Storing and Reading the AD Conversion Result
- 3.23.2.9 Data Polling
- 3.24 Watchdog Timer (Runaway detection timer)
- 3.25 Power Management Circuit (PMC)
- 3.26 Multiply and Accumulate Calculation Unit (MAC)
- 3.27 Debug Mode
- 4. Electrical Characteristics
- 4.1 Maximum Ratings
- 4.2 DC Electrical Characteristics
- 4.3 AC Characteristics
- 4.3.1 Basic Bus Cycle
- 4.3.2 Page ROM Read Cycle
- 4.3.3 SDRAM controller AC Characteristics
- 4.3.4 NAND Flash Controller AC Characteristics
- 4.3.5 Serial channel timing
- 4.3.6 Timer input pulse (TA0IN, TA2IN, TB0IN0, TB1IN0)
- 4.3.7 Interrupt Operation
- 4.3.8 USB Timing (Full-speed)
- 4.3.9 LCD Controller
- 4.3.10 I2S Timing
- 4.3.11 SPI Controller
- 4.4 AD Conversion Characteristics
- 5. Table of Special function registers (SFRs)
- 6. Package
TMP92CZ26A
92CZ26A-5
Figure 1.1 Block Diagram of TMP92CZ26A
(PY)P97
IX
IY
IZ
SP
L H
E D
C B
A W
XSP
XIZ
XIY
XIX
XHL
XDE
XBC
XWA
900/H1 CPU
F SR
32bit
P C
288KB RAM
SERIAL I/O
SIO0
(
RXD0
)
P91
(TXD0)P90
(CTS0, SCLK0)P92
RESET
DBGE
AM
[
1:0
]
10-bit 6ch
AD
Converter
VREFH, VREFL
AVCC, AVSS
(AN3, MY,
ADTRG )PG3
(AN2, MX)PG2
(AN0 to AN1)PG0 to PG1
8BIT TIMER
(TMRA0)
8BIT TIMER
(TMRA1)
(TA1OUT, MLDALM)PM1
8BIT TIMER
(TMRA2)
8BIT TIMER
(TMRA3)
(
TA3OUT
)
PP1
16BIT TIMER
(TMRB0)
WATCH-DOG TIMER
X1
H-OSC
X2
Clock gea
r
Interrupt
Controlle
r
MMU
(TB0OUT0)PP6
XT1
L-OSC
X
T2
(PX, INT4)P96
Touch Screen
I/F
(TSI)
LCD
Controller
(
LCP0
)
PK0
(
LLOAD
)
PK1
(
LFR
)
PK2
(
LVSYNC
)
PK3
(SDA)PV
6
(SCL)PV
7
SDRAM
Controller
(
SDCLK
)
PF7
(
SDRAS
,
SRLLB
)PJ0
(
SDCAS
,
SRLUB
)PJ1
(
SDWE
,
SRWR
)PJ2
(SDLLDQM)PJ3
(
SDLUDQM
)
PJ4
(
SDCKE
)
PJ7
PORT8
P80 (
0CS
)
P81 (
1CS
,
SDCS
)
P82 (
2CS
,
CSZA
,
SDCS
)
P83 (
3CS
,
CSXA
)
P84 (
CSZB
)
P85
(
CSZC
)
PORT1
PORT6
D0 to D7
P10 to P17 (D8 to D15)
PORT7
P70 ( RD )
P73 (EA24)
P74 (EA25)
P75(R/
W , NDR/ B )
P76 (
WAIT )
RTC
MELODY/
ALARM-OUT
KEY-BOARD
I/F
PA0 to PA7 (KI0 to KI7)
PN0 to PN7 (KO0 to KO7)
PC7 (KO8)
PM2
(
ALARM ,MLDALM
)
I
2
S
(I
2
S0)
PLL
NAND-FLASH
I/F (2ch)
(
I2S0DO
)
PF1
(I2S0CKO)PF0
PC4 (EA26)
PC5 (EA27)
PC6 (EA28)
SBI (I
2
Cbus)
(
I2S0WS
)
PF2
SPI
Controller
(SPDO)PR1
(SPDI)PR0
(SPCLK)PR3
(
SPCS
) PR2
(
AN4 to AN5
)
PG4 to PG5
I
2
S
(I
2
S1)
(
I2S1DO
)
PF4
(I2S1CKO)PF3
(
I2S1WS
)
PF5
(TA0IN, INT1)PC1
(TA2IN, INT3)PC3
8BIT TIMER
(TMRA4)
8BIT TIMER
(TMRA5)
(TA5OUT)PP2
8BIT TIMER
(TMRA6)
8BIT
TIMER
(TMRA7)
(
TA7OUT
,
INT5
)
PP3
(TB0IN0, INT6)PP4
16BIT TIMER
(TMRB1)
(TB1OUT0)PP7
(TB1IN0, INT7)PP5
D+
D -
USB
Controlle
r
(X1USB) PX
5
(
LHSYNC
)
PK4
(
LGOE2 to 0
)
PK7 to 5
(
LD7 to 0
)
PL7 to 0
(
LD15 to 8
)
PT7 to 0
(
LD22 to 16
)
PU6 to 0
PC0 (INT0)
PC2
(
INT2
)
P71 ( WRLL , NDRE )
P72 (
WRLU
, NDWE )
P86 (
CSZD
,
CE0ND
)
P87 (
CSXB
,
CE1ND
)
PJ5 (NDALE)
PJ6
(
NDCLE
)
PX7
(
CLKOUT
,
LDIV
)
PX4
PV0 (SCLK0)
PV1
PV2
PW7 to 0
DSU
PZ0 (EI_PODDATA)
PZ1 (EI_SYNCLK)
PZ2 (EI_PODREQ)
PZ3(EI_REFCLK)
PZ4(EI_TRGIN)
PZ5(EI_COMRESET)
PZ6(EO_MCUDATA)
PZ7(EO_MCUREQ)
PMC
PM7 (PWE)
DVCC3A [12]
DVCC3B [1]
DVCC1A [5]
DVCC1B [1]
DVSSCOM
DVCC1C [1]
DVSS1C [1]
BOOT ROM 8KB
MAC
DMAC
PORT5
PORT4
P60 to P67
(
A16 to A23
)
P50 to P57
(
A8 to A15
)
P40 to P47
(
A0 to A7
)
(
LD23, EO_TRGOUT
)
PU7
PORTV
PV3
PV4