User's Manual

Video Display FIFO Registers
Video Display Port4-96 SPRU629
4.14 Video Display FIFO Registers
The display FIFO mapping registers are listed in Table 4–35. These registers
provide DMA write access to the display FIFOs. These pseudo-registers
should be mapped into DSP memory space rather than configuration register
space in order to provide high-speed access. See the device-specific data-
sheet for the memory address of these registers.
The function of the video display FIFO mapping registers is listed in
Table 4–36.
Table 4–35. Video Display FIFO Registers
Acronym Register Name
YDSTA Y FIFO Destination Register A
CBDST Cb FIFO Destination Register
CRDST Cr FIFO Destination Register
YDSTB
Y FIFO Destination Register B
Table 4–36. Video Display FIFO Registers Function
Display Mode
Register BT.656 or Y/C Raw Data
YDSTx Maps Y display FIFO into the
DSP memory.
Maps data display buffer into
the DSP memory.
CBDST Maps Cb display FIFO into the
DSP memory.
Not used.
CRDST
Maps Cr display FIFO into the
DSP memory.
Not used.
In BT.656 or Y/C display mode, three DMAs move data from the DSP memory
to Y, Cb, and Cr display FIFOs by using the memory-mapped YDSTx, CBDST,
and CRDST registers. The DMA transfers are triggered by the YEVT, CbEVT,
and CrEVT events, respectively.
In raw display mode, one DMA channel moves data from the DSP memory to
the Y display FIFO by using the memory-mapped YDSTx register. The DMA
transfers are triggered by a YEVT event.
The video display FIFO registers are write-only locations. Reads of these
addresses returns arbitrary values and do not affect the status of the display
FIFOs.