Datasheet

XIO3130

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SLLS693F–MAY 2007–REVISED JANUARY 2010

4.2.72 Subsystem Access Register

This register is a read/write register. The contents of this register are aliased to the Subsystem Vendor ID

and Subsystem ID registers at PCI Offsets 84h and 86h for all PCI Express ports.

PCI register offset: E0h

Default value: 0000 0000h

BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Table 4-40. Bit Descriptions – Subsystem Access Register

BIT FIELD NAME ACCESS DESCRIPTION

Subsystem ID. The value written to this field is aliased to the Subsystem ID register at PCI

31:16 SubsystemID rw

Offset 66h. This field is loaded from EEPROM (when present) and reset with PERST.

Subsystem Vendor ID. The value written to this field is aliased to the Subsystem Vendor

15:0 SubsystemVendorID rw ID register at PCI Offset 64h. This field is loaded from EEPROM (when present) and reset

with PERST.

4.2.73 General Control Register

This register is a read/write register that is used to control various functions of the XIO3130.

PCI register offset: E4h

Default value: 0000 0000h

BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Table 4-41. Bit Descriptions – General Control Register

BIT FIELD NAME ACCESS DESCRIPTION

31:3 RSVD r Reserved. When read, these bits return zeros.

2 TI_PROPRIETARY rw TI proprietary. This bit must not be changed from the specified default value.

L1 disable. This bit may be used to disable software-directed L1 entry when in

lower D-states (D1-D3). The value of L1_DISABLE is 0 (the default). Link

1 L1_DISABLE rw power states are managed in accordance with the PCI Express base

specification. When L1_DISABLE is 1, the upstream port of the XIO3130 does

not enter L1 even when directed to do so through software.

0 RSVD r Reserved. When read, this bit returns zero.

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