Datasheet

XIO3130
www.ti.com SLLS693F–MAY 2007–REVISED JANUARY 2010
Table 4-18. Bit Descriptions – Power Management Capabilities Register (continued)
BIT FIELD NAME ACCESS DESCRIPTION
3.3-V
AUX
auxiliary current requirements. This field is hardwired to 3’b000. See PCI Power
8:6 AUX_CURRENT r Management Specification Revision 1.2, Section 3.2.3, Page 26, for mapping this field to specific
current consumption values.
Device-specific initialization. This bit returns 0 when read, which indicates that the XIO3130 does
5 DSI r not require special initialization beyond the standard PCI configuration header before a generic
class driver is able to use it.
4 RSVD r Reserved. When read, this bit returns zero.
PME clock. This bit returns zero, which indicates that the PCI clock is not needed to generate
3 PME_CLK r
PME.
2:0 PM_VERSION r Power management version. This field returns 3’b011, which indicates Revision 1.2 compatibility.
4.2.33 Power Management Control/Status Register
This register determines and changes the current power state of the XIO3130.
PCI register offset: 54h
Register type: Read/Write; Read Only
Default value: 0008h
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
Table 4-19. Bit Descriptions – Power Management Control/Status Register
BIT FIELD NAME ACCESS DESCRIPTION
PME status. This bit is hardwired to 0b since the XIO3130’s upstream port does not generate
15 PME_STAT r
PME regardless of PME_SUPPORT field setting.
Data scale. This 2-bit field returns 0’s when read since the XIO3130 does not use the Data
14:13 DATA_SCALE r
Register.
Data select. This 4-bit field returns 0’s when read since the XIO3130 does not use the Data
12:9 DATA_SEL r
Register
PME enable. This bit enables PME signaling. This bit is hardwired to 0b since the XIO3130’s
8 PME_EN r
upstream port does not generate PME.
7:4 RSVD r Reserved. When read, these bits return zeros.
No soft reset. This bit controls whether the transition from D3hot to D0 resets the state
according to the PCI Power Management Specification Revision 1.2. This bit is hardwired to
1’b1.
3 NO_SOFT_RST r
0 – D3hot to D0 transition causes reset.
1 – D3hot to D0 transition does not cause reset.
2 RSVD r Reserved. When read, this bit returns zero.
Power state. This 2-bit field is used both to determine the current power state of the function
and to set the function into a new power state. This field is encoded as follows:
00 = D0
01 = D1
1:0 PWR_STATE rw
10 = D2
11 = D3
hot
See the Power Management section of this document for information about what the XIO3130
does in these different power states.
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