Datasheet

XIO3130
www.ti.com SLLS693F–MAY 2007–REVISED JANUARY 2010
4.2.17 Secondary Status Register .................................................................................... 42
4.2.18 Memory Base Register ......................................................................................... 43
4.2.19 Memory Limit Register ......................................................................................... 43
4.2.20 Pre-fetchable Memory Base Register ........................................................................ 43
4.2.21 Pre-Fetchable Memory Limit Register ....................................................................... 44
4.2.22 Pre-Fetchable Base Upper 32 Bits Register ................................................................ 44
4.2.23 Pre-fetchable Limit Upper 32 Bits Register ................................................................. 45
4.2.24 I/O Base Upper 16 Bits Register ............................................................................. 45
4.2.25 I/O Limit Upper 16 Bits Register .............................................................................. 45
4.2.26 Capabilities Pointer Register .................................................................................. 46
4.2.27 Interrupt Line Register ......................................................................................... 46
4.2.28 Interrupt Pin Register .......................................................................................... 46
4.2.29 Bridge Control Register ........................................................................................ 46
4.2.30 Capability ID Register .......................................................................................... 48
4.2.31 Next-Item Pointer Register .................................................................................... 48
4.2.32 Power Management Capabilities Register .................................................................. 48
4.2.33 Power Management Control/Status Register ............................................................... 49
4.2.34 Power Management Bridge Support Extension Register .................................................. 50
4.2.35 Power Management Data Register ........................................................................... 50
4.2.36 MSI Capability ID Register .................................................................................... 50
4.2.37 Next-Item Pointer Register .................................................................................... 50
4.2.38 MSI Message Control Register ............................................................................... 51
4.2.39 MSI Message Address Register .............................................................................. 51
4.2.40 MSI Message Upper Address Register ...................................................................... 52
4.2.41 MSI Message Data Register .................................................................................. 52
4.2.42 Capability ID Register .......................................................................................... 52
4.2.43 Next-Item Pointer Register .................................................................................... 53
4.2.44 Subsystem Vendor ID Register ............................................................................... 53
4.2.45 Subsystem ID Register ........................................................................................ 53
4.2.46 PCI Express Capability ID Register .......................................................................... 53
4.2.47 Next-Item Pointer Register .................................................................................... 54
4.2.48 PCI Express Capabilities Register ........................................................................... 54
4.2.49 Device Capabilities Register .................................................................................. 54
4.2.50 Device Control Register ....................................................................................... 55
4.2.51 Device Status Register ......................................................................................... 56
4.2.52 Link Capabilities Register ...................................................................................... 57
4.2.53 Link Control Register ........................................................................................... 58
4.2.54 Link Status Register ............................................................................................ 59
4.2.55 Serial Bus Data Register ...................................................................................... 59
4.2.56 Serial Bus Index Register ..................................................................................... 59
4.2.57 Serial Bus Slave Address Register ........................................................................... 60
4.2.58 Serial Bus Control and Status Register ...................................................................... 60
4.2.59 Upstream Port Link PM Latency Register ................................................................... 61
4.2.60 Global Chip Control Register .................................................................................. 63
4.2.61 GPIO A Control Register ...................................................................................... 64
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