Datasheet

XIO2213B

SCPS210F –OCTOBER 2008–REVISED MAY 2013

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Table 3-4. EEPROM Register Loading Map (continued)

SERIAL EEPROM

BYTE DESCRIPTION

WORD ADDRESS

26h PCI 2Fh, subsystem ID, byte 1

[7] [6] [5:3] [2] [1] [0]

Link_Enh enab_unfair HC Control RSVD Link_Enh Link_Enh enab_accel RSVD

27h

Program Phy

Enable

28h Mini-ROM address, this byte indicates the MINI ROM offset into the EEPROM

00h = No MINI ROM

01h to FFh = MINI ROM offset

29h OHCI 24h, GUIDHi, byte 0

2Ah OHCI 25h, GUIDHi, byte 1

2Bh OHCI 26h, GUIDHi, byte 2

2Ch OHCI 27h, GUIDHi, byte 3

2Dh OHCI 28h, GUIDLo, byte 0

2Eh OHCI 29h, GUIDLo, byte 1

2Fh OHCI 2Ah, GUIDLo, byte 2

30h OHCI 2Bh, GUIDLo, byte 3

31h Reserved — no bits loaded

32h PCI F5h, Link_Enh, byte 1, bits 7, 6, 5, 4

33h PCI F0h, PCI miscellaneous, byte 0, bits 7, 4, 2, 1, 0

34h PCI F1h, PCI miscellaneous, byte 1, bits 1, 0

35h Reserved — no bits loaded

36h Reserved — no bits loaded

37h Reserved — no bits loaded

38h Reserved — no bits loaded

39h Reserved multifunction select register

3Ah End-of-list indicator (80h)

This format must be explicitly followed for the bridge to correctly load initialization values from a serial

EEPROM. All byte locations must be considered when programming the EEPROM.

The serial EEPROM is addressed by the bridge at slave address 1010 000b. This slave address is

internally hardwired and cannot be changed by the system designer. Therefore, all three hardware

address bits for the EEPROM are tied to V

to achieve this address. The serial EEPROM in the sample

application circuit (Figure 3-6) assumes the 1010b high-address nibble. The lower three address bits are

terminal inputs to the chip, and the sample application shows these terminal inputs tied to V

During an EEPROM download operation, bit 4 (ROMBUSY) in the serial-bus control and status register is

asserted. After the download is finished, bit 0 (ROM_ERR) in the serial-bus control and status register

may be monitored to verify a successful download.

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