Datasheet

XIO2001
SCPS212G –MAY 2009–REVISED DECEMBER 2012 www.ti.com
4-30 Link Status Register Description .............................................................................................. 68
4-31 Serial-Bus Slave Address Register Descriptions ............................................................................ 70
4-32 Serial-Bus Control and Status Register Description ........................................................................ 70
4-33 GPIO Control Register Description ............................................................................................ 71
4-34 GPIO Data Register Description ............................................................................................... 72
4-35 Control and Diagnostic Register 0 Description .............................................................................. 72
4-36 Control and Diagnostic Register 1 Description .............................................................................. 73
4-37 Control and Diagnostic Register 2 Description .............................................................................. 74
4-38 Subsystem Access Register Description ..................................................................................... 75
4-39 General Control Register Description ......................................................................................... 76
4-40 Clock Control Register Description ............................................................................................ 78
4-41 Clock Mask Register Description .............................................................................................. 79
4-42 Clock Run Status Register Description ....................................................................................... 80
4-43 Clock Control Register Description ............................................................................................ 81
4-44 Arbiter Request Mask Register Description .................................................................................. 83
4-45 Arbiter Time-Out Status Register Description ............................................................................... 84
4-46 Serial IRQ Mode Control Register Description .............................................................................. 85
4-47 Serial IRQ Edge Control Register Description ............................................................................... 85
4-48 Serial IRQ Status Register Description ....................................................................................... 87
4-49 Pre-Fetch Agent Request Limits Register Description ..................................................................... 89
4-50 Cache Timer Transfer Limit Register Description ........................................................................... 90
4-51 Cache Timer Lower Limit Register Description .............................................................................. 90
4-52 Cache Timer Upper Limit Register Description .............................................................................. 90
5-1 PCI Express Extended Configuration Register Map......................................................................... 91
5-2 Uncorrectable Error Status Register Description ............................................................................ 92
5-3 Uncorrectable Error Mask Register Description ............................................................................. 93
5-4 Uncorrectable Error Severity Register Description .......................................................................... 94
5-5 Correctable Error Status Register Description ............................................................................... 95
5-6 Correctable Error Mask Register Description ................................................................................ 96
5-7 Advanced Error Capabilities and Control Register Description ........................................................... 97
5-8 Secondary Uncorrectable Error Status Register Description .............................................................. 98
5-9 Secondary Uncorrectable Error Mask Register Description ............................................................... 99
5-10 Secondary Uncorrectable Error Severity Register Description .......................................................... 100
5-11 Secondary Error Capabilities and Control Register Description ......................................................... 101
5-12 Secondary Header Log Register Description .............................................................................. 102
6-1 Device Control Memory Window Register Map............................................................................. 103
6-2 GPIO Control Register Description .......................................................................................... 104
6-3 GPIO Data Register Description ............................................................................................. 105
6-4 Serial-Bus Slave Address Register Descriptions .......................................................................... 106
6-5 Serial-Bus Control and Status Register Description ....................................................................... 107
6-6 Serial IRQ Mode Control Register Description ............................................................................. 108
6-7 Serial IRQ Edge Control Register Description ............................................................................. 109
6-8 Serial IRQ Status Register Description ..................................................................................... 110
6-9 Pre-Fetch Agent Request Limits Register Description .................................................................... 112
6-10 Cache Timer Transfer Limit Register Description ......................................................................... 113
6-11 Cache Timer Lower Limit Register Description ............................................................................ 114
6-12 Cache Timer Upper Limit Register Description ............................................................................ 114
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