Datasheet

XIO2001
SCPS212G –MAY 2009–REVISED DECEMBER 2012 www.ti.com
4.57 Serial-Bus Slave Address Register
The serial-bus slave address register indicates the slave address of the device being targeted by the
serial-bus cycle. This register also indicates if the cycle is a read or a write cycle. Writing to this register
initiates the cycle on the serial interface. See Table 4-31 for a complete description of the register
contents.
PCI register offset: B2h
Register type: Read/Write
Default value: 00h
BIT NUMBER 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0
Table 4-31. Serial-Bus Slave Address Register Descriptions
BIT FIELD NAME ACCESS DESCRIPTION
7:1
(1)
SLAVE_ADDR RW Serial-bus slave address. This 7-bit field is the slave address for a serial-bus read or write
transaction. The default value for this field is 000 0000b.
0
(1)
RW_CMD RW Read/write command. This bit determines if the serial-bus cycle is a read or a write cycle.
0 = A single byte write is requested (default).
1 = A single byte read is requested.
(1) These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
4.58 Serial-Bus Control and Status Register
The serial-bus control and status register controls the behavior of the serial-bus interface. This register
also provides status information about the state of the serial bus. See Table 4-32 for a complete
description of the register contents.
PCI register offset: B3h
Register type: Read-only, Read/Write, Read/Clear
Default value: 00h
BIT NUMBER 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0
Table 4-32. Serial-Bus Control and Status Register Description
BIT FIELD NAME ACCESS DESCRIPTION
7
(1)
PROT_SEL RW Protocol select. This bit selects the serial-bus address mode used.
0 = Slave address and word address are sent on the serial-bus (default)
1 = Only the slave address is sent on the serial-bus
6 RSVD R Reserved. Returns 0b when read.
5
(1)
REQBUSY RU Requested serial-bus access busy. This bit is set when a software-initiated serial-bus cycle
is in progress.
0 = No serial-bus cycle
1 = Serial-bus cycle in progress
4
(1)
ROMBUSY RU Serial EEPROM access busy. This bit is set when the serial EEPROM circuitry in the bridge
is downloading register defaults from a serial EEPROM.
0 = No EEPROM activity
1 = EEPROM download in progress
3
(1)
SBDETECT RWU Serial Bus Detect. This bit is set when an EEPROM is detected at PERST.
(1) These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
70 Classic PCI Configuration Space Copyright © 2009–2012, Texas Instruments Incorporated
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