Datasheet
XIO2001
www.ti.com
SCPS212G –MAY 2009–REVISED DECEMBER 2012
Table 4-30. Link Status Register Description (continued)
BIT FIELD NAME ACCESS DESCRIPTION
12 SCC R Slot clock configuration. This bit indicates that the bridge uses the same physical reference
clock that the platform provides on the connector. If the bridge uses an independent clock
irrespective of the presence of a reference on the connector, then this bit must be cleared.
0 = Independent 125-MHz reference clock is used
1 = Common 100-MHz reference clock is used
11 LT R Link training. This bit has no function and is read-only 0b.
10 TE R Retrain link. This bit has no function and is read-only 0b.
9:4 NLW R Negotiated link width. This field is read-only 00 0001b indicating the lane width is x1.
3:0 LS R Link speed. This field is read-only 1h indicating the link speed is 2.5 Gb/s.
4.55 Serial-Bus Data Register
The serial-bus data register reads and writes data on the serial-bus interface. Write data is loaded into this
register prior to writing the serial-bus slave address register (offset B2h, see Section 4.57) that initiates the
bus cycle. When reading data from the serial bus, this register contains the data read after bit 5
(REQBUSY) of the serial-bus control and status register (offset B3h, see Section 4.58) is cleared. This
register is reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
PCI register offset: B0h
Register type: Read/Write
Default value: 00h
BIT NUMBER 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0
4.56 Serial-Bus Word Address Register
The value written to the serial-bus word address register represents the word address of the byte being
read from or written to the serial-bus device. The word address is loaded into this register prior to writing
the serial-bus slave address register (offset B2h, see Section 4.57) that initiates the bus cycle. This
register is reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
PCI register offset: B1h
Register type: Read/Write
Default value: 00h
BIT NUMBER 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0
Copyright © 2009–2012, Texas Instruments Incorporated Classic PCI Configuration Space 69
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