Datasheet

XIO2001

SCPS212G –MAY 2009–REVISED DECEMBER 2012

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4.38 Power Management Bridge Support Extension Register

This read-only register indicates to host software what the state of the secondary bus will be when the

bridge is placed in D3. See Table 4-20 for a complete description of the register contents.

PCI register offset: 4Eh

Default value: 40h

BIT NUMBER 7 6 5 4 3 2 1 0

RESET STATE 0 1 0 0 0 0 0 0

Table 4-20. PM Bridge Support Extension Register Description

BIT FIELD NAME ACCESS DESCRIPTION

7 BPCC R Bus power/clock control enable. This bit indicates to the host software if the bus secondary

clocks are stopped when the bridge is placed in D3. The state of the BPCC bit is

controlled by bit 11 (BPCC_E) in the general control register (offset D4h, see

Section 4.65).

0 = The secondary bus clocks are not stopped in D3

1 = The secondary bus clocks are stopped in D3

6 BSTATE R B2/B3 support. This bit is read-only 1b indicating that the bus state in D3 is B2.

5:0 RSVD R Reserved. Returns 00 0000b when read.

4.39 Power Management Data Register

The read-only register is not applicable to the bridge and returns 00h when read.

PCI register offset: 4Fh

Default value: 00h

BIT NUMBER 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 0

4.40 MSI Capability ID Register

This read-only register identifies the linked list item as the register for message signaled interrupts

capabilities. The register returns 05h when read.

PCI register offset: 50h

Default value: 05h

BIT NUMBER 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 1 0 1

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