Datasheet

1.5 V
t
pd
t
pd
Valid
1.5 V
t
on
t
off
Valid
t
su
t
h
CLK
PCI Output
PCI Input
t
w
t
su
CLK
PRST
XIO2001
www.ti.com SCPS212G –MAY 2009–REVISED DECEMBER 2012
Figure 7-3. PRST Timing Waveforms
Figure 7-4. Shared Signals Timing Waveforms
8 Glossary
ACRONYM DEFINTION
BIST Built-in self test
ECRC End-to-end cyclic redundancy code
EEPROM Electrically erasable programmable read-only memory
GP General purpose
GPIO General-purpose input output
ID Identification
IF Interface
IO Input output
I
2
C Intelligent Interface Controller
LPM Link power management
LSB Least significant bit
MSB Most significant bit
MSI Message signaled interrupts
PCI Peripheral component interface
PME PCI power management event
RX Receive
SCL Serial-bus clock
SDA Serial-bus data
TC Traffic class
TLP Transaction layer packet or protocol
TX Transmit
Copyright © 2009–2012, Texas Instruments Incorporated Glossary 123
Submit Documentation Feedback
Product Folder Links: XIO2001