Datasheet

t
wH
2 V
0.8 V
t
rise
t
fall
t
c
t
wL
2 V min Peak-to-Peak
†
C
LOAD
includes the typical load-circuit distributed capacitance.
C
LOAD
Test
Point
Timing
Input
(see Note A )
Out-of-Phase
Output
t
pd
50% V
DD
50% V
DD
V
DD
0 V
0 V
0 V
0 V
0 V
V
OL
t
h
t
su
V
OH
V
OH
V
OL
High-Level
Input
Low-Level
Input
t
w
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
LOAD CIRCUIT
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
INPUT RISE AND FALL TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
t
pd
t
pd
t
pd
V
LOAD
I
OH
I
OL
From Output
Under Test
90% V
DD
10% V
DD
t
f
t
r
Output
Control
(low-level
enabling)
Waveform 1
(see Note B)
Waveform 2
(see Note B)
V
OL
V
OH
V
OH
- 0.3 V
t
PZL
t
PZH
t
PLZ
t
PHZ
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
V
OL
+ 0.3 V
0 V
0 V
≈ 50% V
DD
≈ 50% V
DD
t
en
t
dis
t
pd
t
PZH
t
PZL
t
PHZ
t
PLZ
C
LOAD
†
(pF)
I
OL
(mA)
TIMING
PARAMETER
30/50
12
- 12
0
3
1.5
‡
30/50 12
12
- 12
- 12
LOAD CIRCUIT PARAMETERS
= 50 Ω, where V
OL
= 0.6 V, I
OL
= 12 mA
I
OL
30/50
‡
V
LOAD
- V
OL
I
OH
(mA)
V
LOAD
(V)
Data
Input
In-Phase
Output
Input
(see Note A)
V
DD
V
DD
V
DD
50% V
DD
50% V
DD
50% V
DD
50% V
DD
V
DD
V
DD
50% V
DD
50% V
DD
50% V
DD
50% V
DD
V
DD
50% V
DD
50% V
DD
50% V
DD
50% V
DD
50% V
DD
50% V
DD
50% V
DD
XIO2001
SCPS212G –MAY 2009–REVISED DECEMBER 2012 www.ti.com
7.13 Parameter Measurement Information
PCI Bus
For tPLZ and tPHZ, VOL and VOH are measured values.
Figure 7-1. Load Circuit And Voltage Waveforms
Figure 7-2. CLK Timing Waveform
122 Electrical Characteristics Copyright © 2009–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: XIO2001