Datasheet

7.0 Register Set (Continued)
50
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USBN9603/USBN9604
7.2.26 Receive Data X Register (RXD1, RXD2, RXD3)
Each of the three Receive Endpoint FIFOs has one Receive Data register with the bits defined below.
RXFD
Receive FIFO Data Byte. See “Receive Endpoint FIFO Operation (RXFIFO1, RXFIFO2, RXFIFO3)” in Section 6.2.2 for a
description of Endpoint FIFO data handling.
The firmware should expect to read only the packet payload data. The PID and CRC16 are terminated by the receive state
machine.
7.3 REGISTER MAP
Table 10 lists all device registers, their addresses and their abbreviations.
Table 10. USBN9603/4 Memory Map
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
RXFD
-
r
Address
Register
Mnemonic
Register Name
0x00 MCNTRL Main Control
0x01 CCONF Clock Configuration
0x02 Reserved
0x03 RID Revision Identifier
0x04 FAR Function Address
0x05 NFSR Node Functional State
0x06 MAEV Main Event
0x07 MAMSK Main Mask
0x08 ALTEV Alternate Event
0x09 ALTMSK Alternate Mask
0x0A TXEV Transmit Event
0x0B TXMSK Transmit Mask
0x0C RXEV Receive Event
0x0D RXMSK Receive Mask
0x0E NAKEV NAK Event
0x0F NAKMSK NAK Mask
0x10 FWEV FIFO Warning Event
0x11 FWMSK FIFO Warning Mask
0x12 FNH Frame Number High Byte
0x13 FNL Frame Number Low Byte
0x14 DMACNTRL DMA Control
0x15 DMAEV DMA Event
0x16 DMAMSK DMA Mask
0x17 MIR Mirror
Obsolete