Datasheet

7.0 Register Set (Continued)
31
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USBN9603/USBN9604
Table 5. Interrupt Output Control Bits
7.1.2 Clock Configuration Register (CCONF)
CLKDIV
External Clock Divisor. The power-on reset and a hardware reset configure the divisor to 11
d
(decimal format), which yields
a 4 MHz output clock.
frequency = 48 MHz / (CLKDIV+1)
If the CLKDIV value is changed by firmware, the clock output is expanded/shortened if the CLKDIV value is increased/de-
creased in its current phase, to allow glitch-free switching at the CLKOUT pin.
CODIS
Clock Output Disable. Setting this bit disables the clock output. The CLKOUT output signal is frozen in its current state and
resumes with a new period when this bit is cleared.
7.1.3 Revision Identifier (RID)
This register holds the binary encoded chip revision.
REVID
Revision Identification. For revision 9603 Rev A and 9604 Rev A, the field contains 0010
b
.
INTOC
Interrupt Output
10
0 0 Disabled
0 1 Active low open drain
1 0 Active high push-pull
1 1 Active low push-pull
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
CODIS Reserved CLKDIV3-0
0 - 1011
r/w - r/w
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
Reserved REVID3-0
-0010
-r
Obsolete