Datasheet

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USBN9603/USBN9604

7.0 Register Set

The device has a set of memory-mapped registers that can be read from/written to control the USB interface. Some register

bits are reserved; reading from these bits returns undefined data. Reserved register bits should always be written with 0.

The following conventions are used to describe the register format:

7.1 CONTROL REGISTERS

7.1.1 Main Control Register (MCNTRL)

SRST

Software Reset. Setting this bit causes a software reset of the device. This reset is equivalent to a hardware reset except

that the Clock Configuration (CCONF) register is unaffected. All registers revert to their default values. This bit is cleared

automatically upon completion of the initiated reset.

VGE

Voltage Regulator Enable. Setting this bit enables the internal 3.3V voltage regulator. This bit is hardware reset only to a 0,

disabling the internal 3.3V regulator by default. When the internal 3.3V regulator is disabled, the device is effectively discon-

nected from USB. Upon power-up, the firmware may perform any needed initialization (such as power-on self test) and then

set the VGE bit. Until the VGE bit is set, the upstream hub port does not detect the device presence.

If the VGE bit is reset an external 3.3V power supply may be used on the V3.3 pin.

NAT

Node Attached. This bit indicates that this node is ready to be detected as attached to USB. When reset the transceiver

forces SE0 on the USB port to prevent the hub (to which this node is connected to) from detecting an attach event. After

reset, this bit is left cleared to give the device time before it must respond to commands. After this bit is set, the device no

longer drives the USB and should be ready to receive Reset signaling from the hub.

The NAT bit should be set by the firmware if an external 3.3V supply has been provided to the V3.3 pin, or at least 1 mS

after the VGE bit is set (in the latter case, the delay allows the internal regulator sufficient time to stabilize).

INTOC

Interrupt Output Control. These bits control interrupt ouput according to the following table.

Bit Number bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

Bit Mnemonic Abbreviated bit/ﬁeld names

Corresponding FIFO Corresponding FIFO types and numbers, where relevant

Reset Value reset values, where relevant

r = Read only

w = Write only

r/w = Read and write by ﬁrmware

CoR = Cleared on read

CoW = Cleared on write if written with 0; writing a 1 has no effect

HW = Modiﬁed by the device and by ﬁrmware

bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

INTOC1-0 Reserved NAT VGE Reserved SRST

00 - 00 0

r/w - r/w r/w r/w

Obsolete