Datasheet

CD74HC4051
Vcc
A0 A
Gnd
A1
A2
A3
A7
A5
A6
A7
S1
S0
E
S2
Vee
Temp _1A
Temp _1B
Temp _2A
Temp _2B
Temp _3A
Temp _3B
Temp _4A
Temp _4B
TMUX-2
TMUX-1
TMUX-0
Temperature
+3.3 V
UCD9248
SLVSA33A –JANUARY 2010–REVISED AUGUST 2012 www.ti.com
Figure 12. Temperature Mux (1 rail, 8 phases)
Below is an example of a system with two output voltage rails driven by 3 power stages each. The first output
voltage rail is driven with DPWM-1A, DPWM-1B and DPWM-3A. The second output voltage rail is driven with
DPWM-2A, DPWM-2B and DPWM-4A. The order in which the temperature multiplexer inputs are assigned is
shown in Table 5.
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