Datasheet

FUNCTIONAL OVERVIEW
PMBus Interface
Resistor Programmed PMBus Address Decode
Vdd
10uA
I
BIAS
To12 -bit ADC
Resistorto
setPMBus
Address
On/OffControl
AddrSens0,
AddrSens1
pins
UCD9240
UCD9240
www.ti.com ................................................................................................................................................... SLUS766C – JULY 2008 – REVISED NOVEMBER 2008
PIN DESCRIPTIONS (continued)
64-PIN PACKAGE 80-PIN PACKAGE
I/O DESCRIPTION
PIN NO. SIGNAL PIN NO. SIGNAL
8 DV
SS
9 DV
SS
I Digital ground
26 DV
SS
34 DV
SS
I Digital ground
43 DV
SS
55 DV
SS
I Digital ground
Power It is recommended that this pad be connected to analog ground. (64-pin
No Connect n/a n/a I
Pad package only)
The UCD9240 contains four fusion power peripherals (FPP). Each FPP can be configured to regulated up to four
DC/DC converter outputs. There are eight PWM outputs that can be assigned to drive the coverter outputs. Each
FPP can be configured to drive from one of the eight power stages. Each FPP consists of:
• A differential input error voltage amplifier.
• A 10-bit DAC used to set the output regulation reference voltage.
• A fast ADC with programmable input gain to digitally measure the error voltage.
• A dedicated 3-pole/3-zero digital filter to compensate the error voltage.
• A digital PWM (DPWM) engine that generates the PWM pulse width based on the compensator output.
Each controller is configured through a PMBus serial interface.
The PMBus is a serial interface specifically designed to support power management. It is based on the SMBus
interface that is built on the I
2
C physical specification. The UCD9240 supports revision 1.1 of the PMBus
standard. Wherever possible, standard PMBus commands are used to support the function of the device. For
unique features of the UCD9240, MFR_SPECIFIC commands are defined to configure or activate those features.
These commands are defined in the UCD92xx PMBUS Command Reference.
The UCD9240 is PMBus compliant, in accordance with the "Compliance" section of the PMBus specification. The
firmware is also compliant with the SMBus 1.1 specification, including support for the SMBus ALERT function.
The hardware can support either 100 kHz, 400 kHz, or 1 MHz PMBus operation.
Two pins are allocated to decode the PMBus address. At power-up, the device applies a bias current to each
address detect pin, and the voltage on that pin is captured by the internal 12-bit ADC. The PMBus address is
calculated as follows:
PMBus Address = 12 × bin(V
AD01
) + bin(V
AD00
)
Where bin(V
AD0x
) is the address bin for one of 12 address as shown in Table 1 .
Figure 4. PMBus Address Detection Method
The address bins are defined so that each bin is a constant ratio of the previous bin. This method maintains the
width of each bin relative to the tolerance of the standard 1% resistors. The ratio betweens bins is 1.30.
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