Datasheet

E +
1
2
CV
2
P + CV
2
f
UCD7201
SLUS645E –FEBRUARY 2005–REVISED NOVEMBER 2009 www.ti.com
The CS threshold is 25 mV below the I
LIM
voltage. If the user attempts to command zero current while the CS pin
is at ground the CLF flag will latch high until the IN pin receives a pulse. At start-up it is necessary to ensure that
the ILIM pin will always be greater than the CS pin for the handshaking to work as described below. If for any
reason the CS pin comes to within 25 mV of the ILIM pin during start-up, then the CLF flag will be latched high
and the digital controller must poll the UCD7K device, by sending it a narrow IN pulse. If a fault condition is not
present the IN pulse will reset the CLF signal to low indicating that the UCD7K device is ready to process power
pulses.
Handshaking
The UCD7K family of devices have a built-in handshaking feature to facilitate efficient start-up of the digitally
controlled power supply. At start-up the CLF flag is held high until all the internal and external supply voltages of
the UCD7K device are within their operating range. Once the supply voltages are within acceptable limits, the
CLF goes low and the device will process input drive signals. The micro-controller should monitor the CFL flag at
start-up and wait for the CLF flag to go LOW before sending power pulses to the UCD7K device.
Driver Output
The high-current output stage of the UCD7K device family is capable of supplying ±4-A peak current pulses and
swings to both PVDD and PGND. The driver outputs follow the state of the IN pin provided that the VDD and 3V3
voltages are above their respective under-voltage lockout threshold.
The drive output utilizes Texas Instruments' TrueDrive™ architecture, which delivers rated current into the gate
of a MOSFET when it is most needed, during the Miller plateau region of the switching transition providing
efficiency gains.
TrueDrive™ consists of pullup pulldown circuits with bipolar and MOSFET transistors in parallel. The peak output
current rating is the combined current from the bipolar and MOSFET transistors. This hybrid output stage also
allows efficient current sourcing at low supply voltages.
Each output stage also provides a very low impedance to overshoot and undershoot due to the body diode of the
external MOSFET. This means that in many cases, external-schottky-clamp diodes are not required.
Source/Sink Capabilities During Miller Plateau
Large power MOSFETs present a large load to the control circuitry. Proper drive is required for efficient, reliable
operation. The UCD7K drivers have been optimized to provide maximum drive to a power MOSFET during the
Miller plateau region of the switching transition. This interval occurs while the drain voltage is swinging between
the voltage levels dictated by the power topology, requiring the charging/discharging of the drain-gate
capacitance with current supplied or removed by the driver device. See Reference [1]
Drive Current and Power Requirements
The UCD7K family of drivers can deliver high current into a MOSFET gate for a period of several hundred
nanoseconds. High peak current is required to turn the device ON quickly. Then, to turn the device OFF, the
driver is required to sink a similar amount of current to ground. This repeats at the operating frequency of the
power device.
Reference [1] discusses the current required to drive a power MOSFET and other capacitive-input switching
devices.
When a driver device is tested with a discrete, capacitive load it is a fairly simple matter to calculate the power
that is required from the bias supply. The energy that must be transferred from the bias supply to charge the
capacitor is given by:
(1)
where C is the load capacitor and V is the bias voltage feeding the driver.
There is an equal amount of energy transferred to ground when the capacitor is discharged. This leads to a
power loss given by the following:
(2)
where f is the switching frequency.
8 Submit Documentation Feedback Copyright © 2005–2009, Texas Instruments Incorporated
Product Folder Link(s): UCD7201