Datasheet

UCC2897A
SLUS829D -- AUGUST 2008 -- REVISED JULY 2009
10
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DETAILED PIN DESCRIPTIONS (continued)
CS
This is a direct input to the PWM and current limit comparators of the UCC2897A controller. The CS pin should
never be connected directly across the current sense r esistor (R
CS
) of the power converter. A small, customary
R--C filter between the current sense resistor and the CS pin is necessary to accommodate the proper operation
of the onboard slope compensation circuit and in order to protect the internal discharge transistor connected
to the CS pin (R
F
,C
F
).
Slope compensation is achieved across R
F
by a linearly increasing current flowing out of the CS pin. The slope
compensation current is only present during the on-time of the gate drive signal of the main power switch (OUT)
of the converter. The internal pull-down transistor of the CS pin is activated during the discharge time of the
timing capacitor. This time interval is

1 − D
MAX

× T
SW
long and represents the guaranteed off time of the
main power switch.
RSLOPE
Aresistor(R
SLOPE
) connected between this pin and GND ( pin 6) sets the amplitude of the slope compensation
current. During the on time of the main gate drive output (OUT) the voltage across R
SLOPE
is a representation
of the internal timing capacitor waveform. As the timing capacitor is being charged, the voltage across R
SLOPE
also increases, generating a linearly increasing current waveform. The current provided at the CS pin for slope
compensation is proportional to this current flowing through R
SLOPE
.
Due to the high speed, AC voltage waveform present at the RSLOPE pin, the parasitic capacitance and
inductance o f the external circuit components connected to the RSLOPE pin should be carefully minimized.
For more information on how to program the internal slope compensation refer to the Setup Guide section of
this datasheet.
FB
FB and SS/SD interact. The one with the lower voltage value takes control on the duty cycle, refer to SS/SD
description. This pin is an input for the control voltage of the pulse width modulator of the UCC2897A. The control
voltage is generated by an external error amplifier by c omparing the converters output voltage to a voltage
reference and employing the compensation for the voltage regulation loop. Usually, the error amplifier is located
on the s econdary side of the isolated power converter and its output voltage is sent across the isolation
boundary by an opto coupler. Thus, the FB pin is usually driven by the opto coupler. An external pull-up resistor
to the VREF pin (pin 4) is also needed for proper operation as part of the feedback circuitry.
The control voltage is internally buffered and connected to the PWM comparator through a voltage divider to
make it compatible to the signal level of the current sense circuit. The useful voltage range of the FB pin is
between approximately 2.5 V and 4.5 V. Control voltages below the 2.5-V threshold result in zero duty cycle
(pulse skipping) while voltages above 4.5 V result in full duty cycle (D
MAX
) operation.