Datasheet
UCC1895, UCC2895, UCC3895
www.ti.com
SLUS157P –DECEMBER 1999–REVISED JUNE 2013
RECOMMENDED OPERATING CONDITIONS
(1)
MIN NOM MAX UNIT
V
DD
Supply voltage 10 16.5 V
V
DD
Supply voltage bypass capacitor
(2)
10 × C
REF
C
REF
Reference bypass capacitor (UCC1895)
(3)
0.1 1.0 µF
C
REF
Reference bypass capacitor (UCC2895, UCC3895)
(3)
0.1 4.7
C
T
Timing capacitor (for 500-kHz switching frequency) 220 pF
R
T
Timing resistor (for 500-kHz switching frequency) 82
kΩ
R
DEL_AB
, R
DEL_CD
Delay resistor 2.5 40
T
J
Operating junction temperature
(4)
–55 125 °C
(1) TI recommends that there be a single point grounded between GND and PGND directly under the device. There must be a separate
ground plane associated with the GND pin and all components associated with pins 1 through 12, plus 19 and 20, be located over this
ground plane. Any connections associated with these pins to ground must be connected to this ground plane.
(2) The V
DD
capacitor must be a low ESR, ESL ceramic capacitor located directly across the VDD and PGND pins. A larger bulk capacitor
must be located as physically close as possible to the V
DD
pins.
(3) The V
REF
capacitor must be a low ESR, ESL ceramic capacitor located directly across the REF and GND pins. If a larger capacitor is
desired for the V
REF
then it must be located near the V
REF
cap and connected to the V
REF
pin with a resistor of 51 Ω or greater. The bulk
capacitor on V
DD
must be a factor of 10 greater than the total V
REF
capacitance.
(4) TI does not recommended that the device operate under conditions beyond those specified in this table for extended periods of time.
ELECTRICAL CHARACTERISTICS
V
DD
= 12 V, R
T
= 82 kΩ, C
T
= 220 pF, R
DELAB
= 10 kΩ, R
DELCD
= 10 kΩ, C
REF
= 0.1 μF, C
VDD
= 0.1 μF and no load on the
outputs, T
A
= T
J
. T
A
= 0°C to 70°C for UCC3895x, T
A
= –40°C to +85°C for UCC2895x and T
A
= –55°C to +125°C for the
UCC1895x. (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
UVLO (UNDERVOLTAGE LOCKOUT)
UVLO
(on)
Start-up voltage threshold 10.2 11 11.8
UVLO
(off)
Minimum operating voltage after 8.2 9 9.8
V
start-up
UVLO
(hys)
Hysteresis 1 2 3
SUPPLY
I
START
Start-up current VDD = 8 V 150 250 µA
I
DD
Operating current 5 6 mA
V
DD_CLAMP
V
DD
clamp voltage IDD = 10 mA 16.5 17.5 18.5 V
VOLTAGE REFERENCE
V
REF
Output voltage T
J
= 25°C 4.94 5 5.06
10 V < VDD < V
DD_CLAMP
4.85 5 5.15
V
0 mA < IREF < 5 mA
temperature
I
SC
Short circuit current REF = 0 V, T
J
= 25°C 10 20 mA
ERROR AMPLIFIER
Common-mode input voltage range –0.1 3.6 V
V
IO
Offset voltage –7 7 mV
I
BIAS
Input bias current (EAP, EAN) –1 1 µA
EAOUT
_VOH
High-level output voltage EAP-EAN = 500 mV, I
EAOUT
= –0.5 mA 4 4.5 5
V
EAOUT
_VOL
Low-level output voltage EAP-EAN = –500 mV, I
EAOUT
= 0.5 mA 0 0.2 0.4
I
SOURCE
Error amplifier output source current EAP-EAN = 500 mV, EAOUT = 2.5 V 1 1.5
mA
I
SINK
Error amplifier output sink current EAP-EAN = –500 mV, EAOUT = 2.5 V 2.5 4.5
A
VOL
Open-loop dc gain 75 85 dB
GBW Unity gain bandwidth
(1)
5 7 mHz
Slew rate
(1)
1 V < EAN <0 V, EAP = 500 mV 1.5 2.2 V/µs
0.5 V < EAOUT < 3 V
(1) Ensured by design. Not production tested.
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