Datasheet

GDB
SS
RT
CAOB
GND
VCC
GDA
DMAX
1
2
3
4
5
6
7
8
9
20
19
18
17
16
15
14
13
12
VAO
RDM
PKLMT
RSYNTH
CSA
VSENSE
VINAC
IMO
CDR
10
CSB VREF
CAOA
11
SS
GDB
GND
VCC
GDA
VREF
CAOA
CAOB
VAO
VSENSE
VINAC
IMO
RSYNTH
CSB
CSA
PKLMT
1
2
3
4
5
6
7
8
16
15
14
13
12
11
9
10
18
17
20
19
DMAX
RT
CDR
RDM
UCC28070
SLUS794E –NOVEMBER 2007–REVISED APRIL 2011 www.ti.com
DEVICE INFORMATION
SOIC-20 Top View, DW Package
TSSOP-20 Top View, PW Package
TERMINAL FUNCTIONS
NAME PIN # I/O DESCRIPTION
Dither Rate Capacitor. Frequency-dithering timing pin. An external capacitor to GND programs
CDR 1 I
the rate of oscillator dither. Connect the CDR pin to the VREF pin to disable dithering.
Dither Magnitude Resistor. Frequency-dithering magnitude and external synchronization pin. An
external resistor to GND programs the magnitude of oscillator frequency dither. When frequency
RDM
2 I dithering is disabled (CDR > 5 V), the internal master clock will synchronize to positive edges
(SYNC)
presented on the RDM pin. Connect RDM to GND when dithering is disabled and synchronization
is not desired.
Voltage Amplifier Output. Output of transconductance voltage error amplifier. Internally
VAO 3 O connected to Multiplier input and Zero-Power comparator. Connect the voltage regulation loop
compensation components between this pin and GND.
Output Voltage Sense. Internally connected to the inverting input of the transconductance
voltage error amplifier in addition to the positive terminal of the Current Synthesis difference
VSENSE 4 I
amplifier. Also connected to the OVP, PFC Enable, and slew-rate comparators. Connect to PFC
output with a resistor-divider network.
Scaled AC Line Input Voltage. Internally connected to the Multiplier and negative terminal of the
VINAC 5 I Current Synthesis difference amplifier. Connect a resistor-divider network between V
IN
, VINAC,
and GND identical to the PFC output divider network connected at VSENSE.
Multiplier Current Output. Connect a resistor between this pin and GND to set the multiplier
IMO 6 O
gain.
Current Synthesis Down-Slope Programming. Connect a resistor between this pin and GND to
RSYNTH 7 I set the magnitude of the current synthesizer down-slope. Connecting RSYNTH to VREF will
disable current synthesis and connect CSA and CSB directly to their respective current amplifiers.
Phase B Current Sense Input. During the on-time of GDB, CSB is internally connected to the
CSB 8 I
inverting input of Phase B’s current amplifier through the current synthesis stage.
Phase A Current Sense Input. During the on-time of GDA, CSA is internally connected to the
CSA 9 I
inverting input of Phase A’s current amplifier through the current synthesis stage.
Peak Current Limit Programming. Connect a resistor-divider network between VREF and this
PKLMT 10 I pin to set the voltage threshold of the cycle-by-cycle peak current limiting comparators. Allows
adjustment for desired ΔI
LB
.
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